Swizzle Logic for Memory Address Mapping to Mitigate Row Hammer
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Solution Overview
Problem
In memory devices, particularly DRAM systems, intermittent failures known as 'row hammer' or '1 row disturb' occur due to repeated access to a single row, causing data corruption in adjacent rows, which can lead to concurrent failures across all memory devices, overwhelming traditional error mitigation mechanisms.
Innovation Solution
Implementing swizzle logic to uniquely map physical addresses to different rows within each memory device, using hardware or software logic to route address signals differently to each memory device, thereby scattering the impact of row hammer conditions across multiple memory devices, reducing the likelihood of simultaneous data corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address mapping is used where the same physical address maps to the same row in all memory devices, then address decoding is simple and straightforward, but row hammer conditions cause simultaneous data corruption in all memory devices
Solution Approach 1:
The patent divides the address space mapping into device-specific segments by applying unique swizzle functions to each memory device. Instead of a uniform mapping across all devices, each device receives a customized address mapping that segments the overall address space, preventing simultaneous row corruption across devices while maintaining individual addressability.
Solution Approach 2:
The patent changes the mapping parameter from a fixed identity mapping to a variable swizzled mapping where the relationship between physical address and row address differs for each memory device. This parameter transformation ensures that repeated access to the same physical address targets different physical rows in different devices, mitigating row hammer effects.
2Reliability
If swizzle logic is implemented to map physical addresses differently to each memory device, then row hammer impact is scattered across multiple devices, but address decoding complexity increases
Solution Approach 1:
The patent introduces swizzle logic as an intermediary component between the address bus and memory devices. This intermediary transforms the physical address into a device-specific row address using unique swizzle functions for each device, thereby scattering row hammer impact while managing complexity through modular address translation.
Solution Approach 2:
The patent creates multiple copies of the address mapping function, with each copy being a unique swizzle function tailored to a specific memory device. Instead of implementing complex conditional logic in a single controller, the system replicates the address translation capability across devices with varying mapping parameters, simplifying the overall architecture.
3Productivity
If all memory devices access the same row in response to a memory command, then command execution is efficient and synchronized, but error recovery becomes impossible when all devices fail concurrently
Solution Approach 1:
The patent introduces asymmetry in the address mapping relationship between physical addresses and row locations across different memory devices. While the command execution remains synchronized, the asymmetric mapping ensures that the same physical address targets different physical rows in different devices, preventing simultaneous failure and enabling error recovery through diversity.
Data Source
AI summary
A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.