Variable-Length Symbol Boundary Circuit for Faster Decoding
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Solution Overview
Problem
The processing time for dividing bit strings in existing decode devices becomes a bottleneck, limiting the throughput of these devices when handling variable length symbols.
Innovation Solution
A decode device with a dividing circuit that includes a first block to calculate boundary information for each bit, a second block to update this information, and a third block to output divided bit strings, allowing for parallel processing and reducing the time required for division operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit string is divided into multiple bit strings for parallel decoding, then the throughput of the decode device is improved, but the processing time for dividing the bit string becomes a bottleneck
Solution Approach 1:
The dividing circuit is segmented into three functional blocks: a first block that calculates boundary information for each bit position, a second block that updates this boundary information through iterative processing, and a third block that performs the actual division based on the computed boundaries. This segmentation allows parallel computation of boundary information across all bit positions simultaneously, rather than sequentially processing each potential division point, thereby reducing the division processing time while maintaining parallel decoding throughput.
Solution Approach 2:
The first block pre-calculates boundary information for all possible bit positions in advance by examining the variable length symbol structure. This preliminary calculation of boundary markers allows the third block to perform division operations quickly by simply following the pre-marked boundaries, rather than performing complex analysis during the division process itself. The boundary information serves as pre-computed guidance that accelerates the division operation.
2Speed
If variable length symbols are processed in parallel, then the decoding speed is improved, but the complexity of the dividing circuit increases
Solution Approach 1:
The boundary information calculation mechanism serves multiple functions: it identifies symbol boundaries for division, provides guidance for parallel decoding boundaries, and enables efficient bit string segmentation. By creating a universal boundary marking system that serves all these purposes simultaneously, the circuit avoids needing separate complex mechanisms for each function, thereby reducing overall circuit complexity while supporting parallel processing of variable length symbols.
Solution Approach 2:
The boundary information acts as an intermediary data structure that mediates between the input bit string and the division operation. Instead of directly implementing complex division logic that would require extensive circuitry, the system introduces boundary information as an intermediate representation that simplifies the division task. This intermediary layer translates the complex variable length symbol structure into simple boundary markers that guide the division process, reducing the complexity of the dividing circuit.
Data Source
AI summary
According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.