Pipelined Symbol Compare Logic for Low-Power Data Stream Matching
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Solution Overview
Problem
Existing feature extraction methods in machine learning and pattern recognition face inefficiencies in processing large streams of data, particularly in determining multiple programmable criteria across multiple input symbols, which can lead to slowed or halted data flow and increased power consumption.
Innovation Solution
An integrated circuit with a pipeline of compare logic stages that processes multiple input symbols in parallel, determining whether each meets programmable criteria and providing indicators to successive stages, allowing for efficient extraction of complex features and reducing power usage by not retaining input data after processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing feature extraction methods process multiple programmable criteria sequentially, then measurement precision is improved, but productivity deteriorates due to slowed data flow
Solution Approach 1:
The processing system is divided into multiple parallel pipeline stages, where each stage handles a specific programmable criteria comparison. This segmentation allows simultaneous processing of multiple criteria without sequential bottlenecks, maintaining both precision and throughput by distributing the measurement task across independent parallel units.
Solution Approach 2:
The patent transitions from sequential single-dimensional processing to parallel multi-dimensional processing by implementing multiple pipeline stages that operate simultaneously. Each stage processes a different criteria in parallel, effectively adding a temporal dimension to the processing architecture that enables concurrent evaluation of multiple features without compromising accuracy.
2Measurement precision
If input data is retained for multiple comparison stages, then measurement precision is improved, but use of energy worsens due to increased power consumption
Solution Approach 1:
The patent extracts and processes only the necessary data elements at each pipeline stage rather than retaining all input data throughout the entire processing chain. Each stage receives and processes only the specific symbols relevant to its criteria comparison, discarding unnecessary data retention and thereby reducing the energy required to maintain data in storage buffers across multiple stages.
Solution Approach 2:
Data is discarded after being processed at each pipeline stage and only recovered (re-introduced) when needed for the next specific comparison. This selective discarding and recovering approach prevents continuous retention of all input data through multiple stages, reducing the cumulative power consumption associated with data storage and maintenance across the processing pipeline.
3Productivity
If multiple input symbols are processed in parallel, then productivity is improved, but device complexity worsens
Solution Approach 1:
Each pipeline stage is designed as a universal compare logic unit that can handle multiple input symbols simultaneously using the same hardware structure. This multi-functional design allows a single standardized stage to process any symbol against its programmable criteria, enabling parallel processing of multiple symbols without proportionally increasing device complexity, as the same logic unit is replicated and reused across stages.
Data Source
AI summary
An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.