Symbol Interference Cancellation Circuit for High-Speed Signal Accuracy

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Solution Overview

Problem

As semiconductor integrated circuits increase in speed, signal transmission and reception also increase, leading to higher interference between symbols, which complicates accurate and fast signal transmission and reception.

Innovation Solution

A symbol interference cancellation circuit is designed to generate interference-cancelled signals by canceling post cursor components using weight application signals and sampling output signals, with multiple interference cancellation circuits and sampling circuits operating in synchronization with different clock signals to effectively remove interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the transmission and reception speed of signal is increased, then the speed parameter is improved, but interference between signal symbols increases causing deterioration in accuracy

Engineering Contradiction:
Improvesignal transmission and reception speedVSAvoidsignal transmission and reception accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent converts the harmful post cursor interference components into useful cancellation signals by sampling them at specific timings and combining them with inverted polarity to eliminate interference at the decision point, thereby enabling high-speed transmission while maintaining accuracy

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Measurement precision

If interference cancellation circuits are added to cancel post cursor components, then signal accuracy is improved, but circuit area and complexity increase

Engineering Contradiction:
Improvesignal reception accuracyVSAvoidcircuit area and structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple interference cancellation operations into a unified circuit structure where sampling outputs from different timings are combined through adders and weight application circuits, achieving comprehensive post cursor cancellation while minimizing the number of separate circuits required

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the interference cancellation process into distinct stages: sampling at multiple timings, weight application to each sample, and combination through addition, allowing each segment to be optimized independently while working together to solve the overall problem

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10284396B2Semiconductor device
Publication Date: 2019.05.07 SK HYNIX INC
  • US10284396B2 patent drawing
  • US10284396B2 patent drawing
  • US10284396B2 patent drawing

AI summary

A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.