Symbol Interference Cancellation Circuit Using CTLE and Shift Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits increase in speed, signal transmission and reception also accelerate, leading to increased symbol interference, which complicates accurate and fast signal transmission and reception.
Innovation Solution
A symbol interference cancellation circuit is designed, incorporating continuous time linear equalizers and multiple interference cancellation circuits with weight application signals and sampling signals to cancel post cursor components of input signals, utilizing shift registers and sampling circuits to generate and shift interference-cancelled signals based on clock and clock bar signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If signal transmission speed is increased, then communication efficiency is improved, but symbol interference between adjacent signals increases
Solution Approach 1:
The patent converts the harmful post-cursor interference components into beneficial cancellation signals by feeding them back through shift registers and combining them with inverted polarity with the original signal. The interference that previously degraded signal quality is now used to actively cancel itself, improving overall signal clarity while maintaining high transmission speeds.
Solution Approach 2:
The patent implements a feedback mechanism where the output signal is delayed using shift registers (providing 1st, 2nd, and 3rd post-cursor components) and fed back to the input stage. This feedback loop allows the system to continuously cancel emerging interference components, enabling sustained high-speed operation without accumulation of symbol interference.
2Measurement precision
If multiple interference cancellation circuits are added to cancel more post cursor components, then signal accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the interference cancellation function into three distinct parallel circuits, each targeting a specific post-cursor component (1st, 2nd, and 3rd). This segmentation allows independent optimization of each cancellation stage and enables modular design, where each circuit processes a specific delay version of the signal through dedicated shift registers and combinational logic.
Solution Approach 2:
The patent merges multiple interference cancellation operations into a unified parallel processing structure where three cancellation circuits operate simultaneously on different delayed versions of the signal. The results are then combined through addition circuits, achieving comprehensive interference cancellation while maintaining organized circuit architecture that avoids excessive complexity.
Data Source
AI summary
A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.