Symbol-Level Interleaving for Full-Duplex Slot Interference

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Solution Overview

Problem

Existing full-duplex wireless communication systems do not effectively utilize interleaving techniques, leading to reduced performance and potential interference, especially in half-duplex operations.

Innovation Solution

Implementing symbol level interleaving schemes that differentiate between full-duplex and half-duplex symbols within a slot, allowing for the use of specific interleaving types based on the symbol type, thereby reducing interference and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single interleaving type is used for all symbols in full-duplex slots, then device complexity is reduced, but interference management performance deteriorates

Engineering Contradiction:
Improveinterleaving management complexityVSAvoidinterference management performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the slot into different symbol types (full-duplex symbols and half-duplex symbols) and applies different interleaving types to each segment. This allows optimized interference management for each symbol type while maintaining overall system organization, resolving the contradiction between complexity and performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different interleaving strategies (first interleaving type for full-duplex symbols, second interleaving type for half-duplex symbols) to different local regions of the transmission structure. This local differentiation enables tailored interference management for each symbol type, improving overall reliability without requiring complete system redesign.

Inventive Principle:
Principle #3Local quality

2Reliability

If symbol level interleaving is implemented for full-duplex operations, then interference management improves, but device complexity increases

Engineering Contradiction:
Improveinterference managementVSAvoidinterleaving implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic selection of interleaving types based on symbol type identification. The device dynamically determines whether each symbol is full-duplex or half-duplex and applies the appropriate interleaving strategy, enabling adaptive interference management that improves reliability while keeping complexity manageable through structured decision-making.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the interleaving parameter (interleaving type) based on the symbol type parameter. By linking the interleaving configuration to the symbol operation mode, the system achieves improved interference management through parameter adaptation without requiring fundamentally new hardware or processing capabilities.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If differentiated interleaving is used for full-duplex and half-duplex symbols, then throughput is improved, but processing complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary identification and classification of symbol types before applying interleaving. By determining the operation mode of each symbol in advance, the system can apply the appropriate interleaving type efficiently, improving throughput through better resource allocation while managing processing complexity through structured preliminary analysis.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12349179B2Symbol level interleaving in full-duplex slots
Publication Date: 2025.07.01 QUALCOMM INC
  • US12349179B2 patent drawing
  • US12349179B2 patent drawing
  • US12349179B2 patent drawing

AI summary

In one aspect, a method of wireless communication includes determining, by a user equipment (UE), one or more full-duplex symbols of a slot and one or more half-duplex symbols of the slot; determining, by the UE, to use a first type of interleaving for the one or more full-duplex symbols and a second type of interleaving for the one or more half-duplex symbols; frequency domain mapping, by the UE, virtual resources of the slot to physical resources of the slot based on the first type of interleaving and the second type of interleaving; and communicating, by the UE, based on the physical resources. Other aspects and features are also claimed and described.