Symbol-Based LDPC Variable Node Updates for NAND Error Correction
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Solution Overview
Problem
Semiconductor memory devices face challenges such as increased variability in memory cell I-V characteristics and susceptibility to data errors due to process, voltage, and temperature variations, as well as increased susceptibility to chip-level and system-level soft errors, particularly from alpha particles and noise sources like inductive or capacitive crosstalk, which affect data storage and transmission reliability.
Innovation Solution
Implementing data protection techniques using iterative low-density parity-check (LDPC) decoding with symbol-based variable node updates and message passing algorithms in semiconductor memory systems, which generate valid codewords by determining data state probabilities based on sensed threshold voltages and utilizing multi-variable nodes to enhance decoding performance and correct data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding with symbol-based variable node updates is implemented, then decoding performance is improved and data errors are reduced, but computational complexity at check nodes increases
Solution Approach 1:
The variable nodes are segmented into multiple sub-variable nodes, each handling a portion of the decoding computation. This segmentation distributes the computational burden across multiple simpler units rather than requiring a single complex check node to perform all computations, thereby reducing the computational complexity at check nodes while maintaining overall decoding performance.
Solution Approach 2:
The patent transitions from traditional binary LDPC decoding to symbol-based LDPC decoding by adding an additional dimension of symbol likelihood information. This dimensional change allows the decoder to process multiple bits per symbol simultaneously, improving decoding performance and error correction capability while the segmented variable node structure manages the resulting computational complexity.
2Quantity of substance
If multi-level memory cells are used to enhance data storage density, then storage capacity increases, but susceptibility to data errors increases due to threshold voltage variability
Solution Approach 1:
The system performs preliminary determination of symbol likelihoods and data state probabilities before the main decoding process. By pre-calculating these probability values based on sensed threshold voltages and storing them in lookup tables, the system prepares correction information in advance, which enables more effective error correction during decoding and compensates for the increased error susceptibility of multi-level memory cells.
Solution Approach 2:
The iterative LDPC decoding process incorporates feedback loops where decoded information is continuously refined across multiple iterations. The symbol-based variable node updates use feedback from check nodes to progressively improve the accuracy of decoded symbols, allowing the system to correct errors that arise from multi-level cell variability and achieve reliable data recovery despite the increased error rate.
Data Source
AI summary
Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.