Symbol Lock Pattern for Memory Data Burst Synchronization
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Solution Overview
Problem
High-speed semiconductor memory devices face challenges in accurately finding the start point of a data burst due to increased interfacing speeds, leading to decreased performance of symbol lock methods, especially in mobile systems where clock signal skew occurs.
Innovation Solution
A memory system that includes a transmitter and receiver, where the transmitter sends a data signal with a symbol lock pattern and a data burst, and the receiver detects the symbol lock pattern to find the start point of the data burst using a clock generator, sampler, write FIFO, symbol lock pattern detector, and data aligner, independent of the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interfacing speed of the memory device is increased, then the data transmission speed is improved, but the accuracy of finding the start point of transmitted data deteriorates
Solution Approach 1:
The patent applies preliminary action by inserting a symbol lock pattern before the actual data burst transmission. This pattern serves as a pre-prepared reference sequence that enables the receiver to synchronize and identify the start point of data before the actual data arrives, thus resolving the timing synchronization issue at high speeds
Solution Approach 2:
The symbol lock pattern acts as an intermediary element between the transmitter and receiver. It provides a known reference sequence that mediates the synchronization process, allowing the receiver to accurately determine the start point of data bursts without being affected by clock signal skew at high transmission speeds
2Speed
If the interfacing speed is increased, then the data transmission performance is improved, but the symbol lock method performance deteriorates
Solution Approach 1:
The symbol lock pattern is transmitted in advance as a preliminary synchronization sequence. This allows the receiver to perform correlation detection and establish timing reference before the actual data burst arrives, ensuring reliable symbol lock performance even at increased interfacing speeds
Solution Approach 2:
The receiver uses correlation detection to compare the received signal with the known symbol lock pattern, providing feedback information about timing synchronization. This feedback mechanism enables the receiver to accurately identify the start point of data bursts and maintain reliable symbol lock performance at high speeds
3Adaptability or versatility
If clock signal skew occurs in mobile systems, then the system adaptability is improved, but the accuracy of symbol lock detection deteriorates
Solution Approach 1:
The symbol lock pattern serves as an intermediary reference that is independent of clock signal synchronization. By correlating the received signal with this known pattern, the receiver can accurately detect the start point of data bursts even when clock signal skew occurs, thus maintaining detection accuracy in mobile systems with varying clock conditions
Solution Approach 2:
The patent changes the detection parameter from clock-synchronized sampling to correlation-based detection using the symbol lock pattern. This parameter change makes the symbol lock detection independent of clock signal timing, allowing accurate detection even when clock skew varies due to mobile system conditions
Data Source
AI summary
A memory system includes a transmitter and a receiver. The transmitter is configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface. The data burst includes a first data and a subsequent data. The receiver is configured to receive the data signal, to detect the first symbol lock pattern based on the received data signal, and to find the first data of the data burst according to the detected first symbol lock pattern.