Symbol Timing Recovery for Parallel Tape Channels

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Solution Overview

Problem

Conventional symbol timing recovery (STR) schemes in tape storage systems with multiple parallel channels face challenges such as cycle slips due to noisy timing estimates, leading to bit loss or insertion errors, especially at low signal-to-noise ratios (SNR), as they rely on independent second-order phase lock loops (PLLs) that fail to maintain accurate sampling.

Innovation Solution

A system and method that utilize a plurality of timing error detectors, loop filters, and interpolation filters to calculate a common phase and skew estimate across multiple read channels, reducing cycle slips by weighting timing-error estimates and adjusting phase estimates for each channel, thereby improving synchronization accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If independent second order PLLs are used for each read channel, then noise rejection is optimized and sampling jitter is minimized, but cycle slip rate increases significantly at low SNR conditions

Engineering Contradiction:
Improvesampling timing accuracyVSAvoidcycle slip rate
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent merges the independent PLL operations across multiple read channels by introducing a common phase estimate that is shared among all channels. Instead of each channel having completely independent timing recovery, the system combines timing error detector outputs across channels and uses a common loop filter to generate a unified phase estimate, thereby reducing cycle slips at low SNR while maintaining sampling accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback by using timing error detector outputs from multiple channels to generate a common phase estimate that feeds back to adjust the sampling timing across all channels. The loop filter processes timing error signals and generates phase corrections that are applied systematically, creating a feedback mechanism that reduces timing errors and cycle slips.

Inventive Principle:
Principle #23Feedback

2Productivity

If track and linear bit density are increased on recording tape, then data storage capacity is improved, but signal-to-noise ratio decreases

Engineering Contradiction:
Improvedata storage densityVSAvoidsignal-to-noise ratio
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent combines information from multiple read channels to improve the overall signal quality. By merging timing error detector outputs across channels and using a common phase estimate, the system effectively aggregates signal information, which helps maintain accurate timing recovery even when individual channels suffer from low SNR due to high density recording.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple parallel read channels are used simultaneously, then reading speed is improved, but timing error estimation becomes noisier leading to increased cycle slips

Engineering Contradiction:
Improvereading speedVSAvoidtiming estimation accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges the timing recovery operations across multiple parallel read channels by introducing a common phase estimate mechanism. Instead of treating each channel's timing errors independently, the system combines timing error detector outputs from all channels and processes them through a common loop filter, thereby reducing the noise in timing estimation and reducing cycle slips while maintaining high reading speeds.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback by systematically using timing error signals from all channels to generate phase corrections that feed back to adjust sampling timing across the board. This feedback mechanism allows the system to correct timing errors collectively, improving timing estimation accuracy even when multiple channels operate simultaneously at high speeds.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9251811B1Symbol timing recovery scheme for parallel recording channel systems
Publication Date: 2016.02.02 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9251811B1 patent drawing
  • US9251811B1 patent drawing
  • US9251811B1 patent drawing

AI summary

A method for symbol timing recovery is disclosed. The method comprises receiving a plurality of timing-error estimates for a plurality of read channels, where each of the timing-error estimates corresponds to one of the read channels. The method further comprises calculating a common phase based on the plurality of timing-error estimates, and calculating a skew of a transducer array based on the plurality of timing-error estimates. Finally, the method comprises calculating a different total phase estimate for each read channel based on the calculated common phase and the calculated skew of the transducer array.