Symbolic Connectivity for RTL-Layout Equivalency Verification
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Solution Overview
Problem
Conventional integrated circuit design processes often result in a mismatch between the Register Transfer Level (RTL) and physical layout due to placement, route topologies, and clock loading constraints, leading to a lack of equivalency between logical and physical designs.
Innovation Solution
A method is provided to maintain symbolic connectivity by generating a netlist representation from a reference RTL design, updating the physical layout, and using design verification tools to ensure consistency and equivalency between the layout, symbolic connectivity, and RTL, allowing for parallel modifications and verification at various design stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If placement, route topologies, and clock loading constraints are optimized for performance, then timing performance is improved, but equivalency between RTL and layout deteriorates
Solution Approach 1:
The patent introduces symbolic connectivity as an intermediary representation that bridges RTL and physical layout. This symbolic netlist maintains the logical connectivity information from RTL while being updated in parallel with physical design changes, allowing equivalency verification without requiring direct RTL-layout comparison that would be disrupted by performance optimizations
Solution Approach 2:
The patent implements a feedback mechanism where design verification tools continuously check consistency between layout, symbolic connectivity, and reference RTL. This feedback loop detects deviations caused by placement and routing optimizations and enables corrective actions to maintain equivalency while preserving performance benefits
2Adaptability or versatility
If aggressive integration methodology is used to optimize performance, then design flexibility is improved, but mismatch between RTL and layout increases
Solution Approach 1:
The patent makes the symbolic connectivity dynamic by updating it in parallel with physical design changes rather than maintaining a static reference schematic. This dynamic update approach allows the system to adapt to placement, routing, and clock loading changes while continuously maintaining equivalency information for verification
Solution Approach 2:
Symbolic connectivity serves as a flexible intermediary that can accommodate various physical design methodologies while maintaining the logical design intent. It allows aggressive integration and performance optimization without permanently breaking the traceability to RTL specifications
3Ease of manufacture
If reference schematic is not maintained due to layout modifications, then design updates are simplified, but verification capability is reduced
Solution Approach 1:
Instead of maintaining a single reference schematic that becomes outdated, the patent creates and maintains a symbolic connectivity representation that is updated in parallel with physical design changes. This copying approach preserves the verification capability without requiring manual updates to reference schematics
Solution Approach 2:
The patent performs preliminary actions by generating symbolic connectivity from the reference RTL early in the design process, before physical design modifications occur. This early establishment of the symbolic model allows subsequent parallel updates without losing the ability to verify equivalency
Data Source
AI summary
A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity.