Symbolic QED for Post-Silicon Logic Bug Localization
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Solution Overview
Problem
Current post-silicon validation and debug methods for integrated circuits and systems-on-a-chip are inefficient, requiring extensive time and manual intervention, and often fail to adequately detect and localize logic bugs due to reliance on failure reproduction and trace buffers.
Innovation Solution
The introduction of Symbolic Quick Error Detection (QED) methods, which automate bug localization by inserting 'change detectors' and using formal techniques to generate minimal bug traces without requiring human intervention or trace buffers, allowing for quick error detection and localization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional post-silicon validation methods are used, then bug detection capability is maintained, but bug localization time increases significantly (days or weeks)
Solution Approach 1:
The patent inserts change detectors and instrumentation code into the binary image during the build process, before the software is deployed to the device. This preliminary action prepares the system for rapid bug localization without requiring additional setup time during actual debugging, enabling the system to automatically capture and report bug traces when errors occur.
Solution Approach 2:
The patent introduces change detectors as intermediary components that monitor and track state changes in the system. These detectors act as mediators between the underlying hardware/software and the debugging process, automatically capturing bug traces and providing localized information without requiring manual intervention or full system trace analysis.
2Extent of automation
If manual bug localization methods are used, then comprehensive analysis is possible, but human intervention is required which reduces productivity
Solution Approach 1:
The patent implements a self-service debugging system where change detectors automatically monitor system state, identify bugs, capture traces, and report localized information without human intervention. The system serves itself by automatically instrumenting the binary, monitoring execution, and providing bug localization results, eliminating the need for manual analysis and significantly improving debugging productivity.
Solution Approach 2:
The patent establishes a feedback mechanism where change detectors continuously monitor system state and provide immediate feedback when bugs are detected. The system automatically captures bug traces and feeds this information back to the debugging process, enabling rapid identification and localization of issues without requiring manual intervention at each step.
3Device complexity
If trace buffers are used for bug detection, then bug traces can be captured, but device area increases and complexity is introduced
Solution Approach 1:
The patent extracts the bug detection and tracing functionality from complex hardware trace buffers and implements it through software-based change detectors inserted into the binary image. This extraction eliminates the need for large hardware trace buffer structures while maintaining the ability to capture and report bug traces, thereby reducing device area and hardware complexity while preserving bug detection reliability.
Solution Approach 2:
The patent creates a software-based copy of the trace buffering functionality through change detectors that are inserted into the binary image. Instead of using physical hardware trace buffers, the system uses software instruments that replicate the tracing capability, significantly reducing hardware area requirements while maintaining the ability to capture bug traces for analysis.
Data Source
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AI summary
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called "change detectors" which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting "change detectors" during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection.