Symbolic Simulation for HDL Verification
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Solution Overview
Problem
Current digital circuit design verification methods, such as concrete simulation, are limited by the need for manual input creation and are inefficient due to the complexity of modern digital circuits, making exhaustive testing impractical, especially for high-speed circuits.
Innovation Solution
A method for symbolic simulation that generates a binary simulation of digital circuit designs, using control and program states with symbolic signal values, allowing for the identification of combinational logic expressions and next state functions, enabling more efficient verification by generalizing execution time and signal values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If concrete simulation is used to verify digital circuits, then the circuit operation can be tested, but the testing completeness depends on designer skill and cannot cover all possible inputs
Solution Approach 1:
The symbolic simulation system automatically generates test vectors and verifies circuit behavior without requiring manual test construction. The system serves itself by using the circuit's own logic expressions to generate comprehensive test cases, eliminating the need for designer expertise in creating exhaustive test suites.
Solution Approach 2:
Symbolic values act as an intermediary between concrete test inputs and circuit verification. Instead of directly applying concrete values, the system uses symbolic representations that can represent multiple values simultaneously, allowing automatic generation of comprehensive test coverage without manual intervention.
2Reliability
If concrete simulation tests one cycle per simulation cycle, then circuit response can be recorded, but the simulation speed is extremely slow (1 Hz vs gigahertz operation)
Solution Approach 1:
The system changes the parameter representation from concrete values to symbolic expressions. This allows the simulation to operate on algebraic representations of circuit behavior rather than step-by-step concrete values, enabling mathematical analysis of the entire circuit operation without being constrained by real-time simulation speed limitations.
Solution Approach 2:
The invention transitions from temporal simulation (cycle-by-cycle execution) to a mathematical dimension where circuit behavior is analyzed through logic expressions and symbolic computation. This dimensional shift allows verification of gigahertz-speed circuits using methods not bound by real-time execution constraints.
3Reliability
If gate-level netlists are used for model checking, then exhaustive verification is possible, but the translation from HDL RTL is limited and does not fully preserve behavior
Solution Approach 1:
The system creates a symbolic copy of the HDL RTL description that preserves the original behavior and semantics. Instead of translating to gate-level netlists that may lose information, the invention maintains a symbolic representation that is mathematically equivalent to the original HDL code, ensuring complete behavior preservation while enabling exhaustive verification.
Data Source
AI summary
A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.