Symmetric Bit-Stacking Binary Counters for Multiplier Latency
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Solution Overview
Problem
Existing binary counter designs in multiplier circuits face inefficiencies due to delays and power consumption issues caused by chains of XOR gates on the critical path, limiting the speed and power efficiency of multiplier circuits.
Innovation Solution
The implementation of a symmetric bit-stacking approach that eliminates XOR gates and multiplexers on the critical path, allowing for the design of 6:3 and 7:3 counters that reduce latency and power consumption by using bit stacking circuits to efficiently count bits, which are then used in binary multiplier circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional XOR gate chains are used in counter circuits, then the circuit can perform binary counting functions, but the critical path delay increases and speed decreases
Solution Approach 1:
The patent extracts and removes XOR gates from the critical path of the counter circuit. By reconfiguring the counter to use alternative logic structures that eliminate XOR operations from the critical path, the design achieves faster operation without sacrificing counting functionality.
Solution Approach 2:
The counter circuit is segmented into separate functional paths, with the critical path redesigned to avoid XOR gate chains. The counting function is divided such that certain operations occur in parallel or through different logic structures that do not create sequential delays.
2Power
If traditional counter designs are used in multiplier circuits, then the multiplication function can be performed, but power consumption increases
Solution Approach 1:
The patent removes multiplexers from the critical path of the counter circuit. By eliminating these components from the signal path, the design reduces the number of switching operations and associated power consumption, particularly in high-speed multiplier circuits where the counter operates frequently.
Solution Approach 2:
The logic structure parameters are changed by replacing traditional XOR gate and multiplexer configurations with alternative logic designs that have lower power consumption characteristics while maintaining the same counting function.
3Device complexity
If XOR gates and multiplexers are used on the critical path, then the counter can be implemented with standard logic, but the circuit complexity and area increase
Solution Approach 1:
The patent extracts multiplexers from the critical path, reducing the number of logic components that signals must pass through. This extraction simplifies the critical path structure and reduces the overall circuit complexity while improving speed.
Data Source
AI summary
In this paper, binary stackers and counters are presented. In an embodiment, a counter uses 3-bit stacking circuits which group T bits together, followed a symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 and 7:3 Counter circuits with no XOR gates on the critical path. This avoids of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the presently-disclosed counters were 30% faster and at consumed at least 20% less power than existing parallel counters. Additionally, using the presently-disclosed counter in existing Counter Based Wallace tree multiplier architectures reduce latency and improves efficiency in term of power-delay product for 64-bit and 128-bit multipliers.