Symmetric Bridge Arm Power Module Reducing Parasitic Inductance
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Solution Overview
Problem
Power converters face challenges in achieving high efficiency and power density due to parasitic inductances in bridge arms, which lead to voltage spikes and electromagnetic interferences, affecting reliability and performance.
Innovation Solution
The design includes symmetrically arranged bridge arms with semiconductor devices connected through common pins, reducing loop inductances and parasitic effects, and the use of capacitance bridge arms to further mitigate inductive influences, resulting in a symmetric circuit structure that minimizes voltage spikes and electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If devices are connected through bonding wires and lead frames, then the power converter can be assembled, but parasitic inductances increase causing voltage spikes and electromagnetic interferences
Solution Approach 1:
The patent merges the connection function of bonding wires and lead frames into an integrated substrate structure. The substrate directly connects the semiconductor devices, eliminating the need for separate bonding wires and lead frames, thereby reducing parasitic inductances and improving power module reliability.
Solution Approach 2:
The patent extracts and removes the bonding wires and lead frames from the traditional connection structure. By eliminating these components, the source of parasitic inductances is removed, reducing voltage spikes and electromagnetic interferences while maintaining device connectivity through the substrate.
2Loss of energy
If efficiency is increased by 1%, then power consumption is reduced by 10%, but achieving higher efficiency requires reducing parasitic effects which complicates the circuit design
Solution Approach 1:
The patent combines multiple functions into the substrate structure, which simultaneously serves as the circuit board, connection medium, and parasitic reduction element. This integration achieves energy loss reduction without proportionally increasing circuit complexity, as the substrate performs multiple roles that would otherwise require separate components.
Solution Approach 2:
The patent changes the physical and electrical parameters of the substrate to optimize performance. By adjusting substrate material properties, thickness, and layout configuration, the patent reduces parasitic inductances and achieves higher efficiency without significantly complicating the overall circuit design.
3Object-generated harmful factors
If symmetric circuit structure is implemented, then voltage spikes are reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent intentionally introduces asymmetric compensation elements in the substrate design to counterbalance the inherent asymmetries in device placement and connections. This approach reduces voltage spikes without requiring extremely high manufacturing precision, as the asymmetric elements are designed to compensate for typical manufacturing variations.
Solution Approach 2:
The substrate design incorporates pre-calculated compensation features that anticipate and cushion against manufacturing tolerances. By designing the substrate with built-in compensation for expected position variations, the patent reduces voltage spikes while maintaining reasonable manufacturing precision requirements.
Data Source
AI summary
A power system, a power module therein and a method for fabricating power module are disclosed herein. The power module includes a first and a second common pins, and a first and a second bridge arms. The first and the second common pins are symmetrically disposed at one side of a substrate. The first bridge arm includes a first and a second semiconductor devices, and the first and the second semiconductor devices are connected to each other through the first common pin and disposed adjacently. The second bridge arm includes a third and a fourth semiconductor devices, and the third and the fourth semiconductor devices are connected to each other through the second common pin and disposed adjacently. The first and the third semiconductor devices are disposed symmetrically, and the second and the fourth semiconductor devices are disposed symmetrically.