Capacitive-Coupled Level Shifter With Symmetric Divider Branches
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Solution Overview
Problem
Existing level shifter designs for high-speed gate driver applications face challenges in achieving high common mode rejection, speed performance, and minimizing layout area, especially when operating at high voltages beyond the breakdown capability of available devices, while also dealing with noise and temperature variations.
Innovation Solution
A capacitive-coupled level shifter design that includes a capacitive divider circuit and a comparator circuit to shift signals from a low voltage domain to a higher voltage domain, using capacitors to block DC components and convert static control signals into continuous sequences of pulses, thereby reducing false triggering due to noise, and incorporating a resistor ladder for DC biasing and a speed booster circuit for increased gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If cascoding approach is used to handle high voltage range, then voltage handling capability is improved, but speed performance deteriorates and layout area increases
Solution Approach 1:
The circuit is divided into two separate voltage domains (first voltage domain with lower voltage and second voltage domain with higher voltage), each handled by dedicated circuits. The capacitive coupling mechanism segments the voltage handling function, allowing each domain to operate independently at optimized speeds without the degradation caused by cascading high-voltage devices.
2Strength
If cascoding approach is used to handle high voltage range, then voltage handling capability is improved, but layout area increases
Solution Approach 1:
By segmenting the circuit into two voltage domains separated by capacitive coupling, the layout can be optimized for each domain independently. Low-voltage components require smaller areas, and the capacitive coupling structure occupies less space than the stacked high-voltage device configuration required by cascoding.
3Reliability
If transformer or capacitor based level shifting is used for high speed applications, then common mode rejection is improved, but current consumption increases
Solution Approach 1:
The circuit parameters (capacitance values, voltage domain levels, switching frequencies) are optimized to achieve the desired common mode rejection performance while minimizing current consumption. The capacitive coupling allows AC signal transmission with high common mode rejection while the DC biasing is maintained at minimal current levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive-coupled level shifter achieves higher speed performance, reduced dependency on temperature and process variations, and smaller chip area, with improved common mode rejection and power supply rejection ratio, effectively handling high-speed and high-power applications with enhanced reliability and noise immunity.
Implementation Method 1
a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit
Data Source
AI summary
A capacitive-coupled level shifter includes: an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of the modulated signal. A level shifter system which includes the capacitive-coupled level shifter is also described.