Semiconductor Gate Layout for Symmetric Channel Formation

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Solution Overview

Problem

The asymmetry in the effective channel region caused by different mask patterns for ion implantation processes in semiconductor devices like SJMOSFETs affects the threshold voltage characteristics, leading to uneven distribution.

Innovation Solution

Using the same mask pattern for both the body and impurity regions during ion implantation, followed by thermal processes to form overlapping regions with intersecting directions, and additional ion implantations using gate electrodes as masks to ensure symmetry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If different mask patterns are used for ion implantation processes for the body region and the impurity region, then the ion implantation can be performed with optimized patterns for each region, but asymmetry in the effective channel region is caused by process distribution, affecting the threshold voltage characteristics

Engineering Contradiction:
Improveion implantation process flexibilityVSAvoideffective channel region symmetry
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent intentionally introduces asymmetry in the form of a dummy impurity region to compensate for the asymmetry caused by process distribution. This dummy region is formed with a different mask pattern than the main impurity region, creating a deliberate asymmetric structure that balances the overall effective channel region symmetry when both regions are combined

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If the same mask pattern is used for ion implantation processes for the body region and the impurity region, then the threshold voltage distribution is reduced, but the manufacturing process complexity increases

Engineering Contradiction:
Improvethreshold voltage uniformityVSAvoidmask pattern design complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the impurity region formation into two separate implantation processes: a main impurity region formation process and a dummy impurity region formation process. Each process uses its own mask pattern, allowing independent optimization while achieving overall symmetry in the effective channel region

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the threshold voltage distribution, ensuring stable and symmetric channel regions, thereby enhancing the semiconductor device's performance.

Implementation Method 1

performing a first ion implantation for a body region and a first impurity region in the substrate by using the mask pattern

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing a first thermal process on the substrate and forming the body region and the first impurity region

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Data Source

PatentUS20250210354A1Manufacturing method of semiconductor device
Publication Date: 2025.06.26 DONGBU HITEK CO LTD
  • US20250210354A1 patent drawing
  • US20250210354A1 patent drawing
  • US20250210354A1 patent drawing

AI summary

A method of manufacturing a semiconductor device, comprising the steps of: forming a mask pattern on a substrate, performing a first ion implantation for a body region and a first impurity region in the substrate by using the mask pattern, forming a first gate electrode and a second gate electrode spaced apart from each other on the substrate, performing a first thermal process on the substrate and forming the body region and the first impurity region, and forming a contact extending to the first impurity region between the first gate electrode and the second gate electrode.