Symmetric Single-to-Differential Clock Circuit for Low-Skew Output
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Solution Overview
Problem
Designing a single-to-differential circuit with high accuracy in a small layout area is challenging due to the asymmetry and larger size of P-type transistors, which complicates routing and increases layout size.
Innovation Solution
A symmetric single-to-differential circuit design using buffer circuits to enhance the driving capability of inverters, reducing rising and falling times of differential output clock signals, and employing symmetric layout to minimize overall size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If P-type transistors are used in the circuit, then driving capability is improved, but layout area increases due to asymmetry and larger size
Solution Approach 1:
The patent applies asymmetry principle by intentionally using different transistor types (P-type and N-type) with different characteristics in different parts of the circuit to achieve optimal performance. The P-type transistors are used where high driving capability is needed, while N-type transistors are used where compact size is preferred, creating a balanced asymmetric design that resolves the contradiction between driving capability and layout area.
2Reliability
If asymmetric layout is used to accommodate P-type transistors, then circuit functionality is maintained, but routing complexity increases
Solution Approach 1:
The patent applies local quality principle by optimizing the layout and routing in different local regions of the circuit according to specific requirements. In regions with P-type transistors, the layout is designed to accommodate their larger size, while in other regions, compact routing is employed. This localized optimization maintains circuit functionality while managing overall routing complexity.
3Ease of operation
If inverter stages are used for signal conversion, then signal transformation is achieved, but rising time and falling time increase
Solution Approach 1:
The patent applies parameter changes principle by modifying the transistor sizing parameters and circuit configuration parameters in the inverter stages. By optimizing the width-to-length ratios of transistors and adjusting the number of stages, the circuit achieves faster switching speeds while maintaining the required signal conversion capability. This resolves the contradiction between ease of operation and speed.
Data Source
AI summary
The present disclosure provides an integrated circuit, which includes an input stage, a first output stage, and a second output stage. The input stage receives and converts an input clock signal into a first signal and a second signal. The first output stage includes a first inverter and a first buffer circuit. The first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at a first output terminal of the integrated circuit. The second output stage includes a second inverter and a second buffer circuit. The second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at a second output terminal of the integrated circuit. The first output clock signal and the second output clock signal are differential clock signals.