Symmetric Tunable Delay Circuit for Linear Delay Increments
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time delay circuits exhibit nonlinear time delays across various settings due to variations in delay units, leading to inconsistent signal processing in electronic systems.
Innovation Solution
A symmetrically-interconnected tunable time delay circuit is designed with multiple delay units and buffer units, each having a similar output load characteristic, along with a one-hot decoder and an adaptive clock distribution circuit, to ensure quasi-linear time delays and mitigate supply voltage droop by adjusting clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional time delay circuits are used with multiple delay units, then time delay functionality is achieved, but the time delay increments become nonlinear and inconsistent across different delay settings
Solution Approach 1:
Each delay unit is designed with matched output load characteristics (passive load and active load) to ensure uniform signal driving capability. The buffer units are symmetrically interconnected with matched interconnects to a common transmission line, creating local symmetry that compensates for process variations and ensures consistent time delay increments across all delay settings.
Solution Approach 2:
The circuit uses process voltage scaling (PVS) to adjust the operating voltage of delay units and buffer units, thereby changing their delay characteristics. By controlling the voltage parameter, the circuit achieves linearizable time delay where the delay increment becomes consistent across different delay settings, resolving the nonlinearity issue.
2Ease of operation
If multiple buffer units are used to drive different delay outputs, then signal distribution is achieved, but supply voltage droop occurs due to simultaneous switching of multiple buffers
Solution Approach 1:
The adaptive clock distribution circuit distributes clock signals periodically to buffer units in a controlled sequence. Instead of allowing all buffers to switch simultaneously, the system uses periodic clock edges with adjusted frequencies to stagger the switching events, thereby reducing peak current demand and mitigating supply voltage droop while maintaining signal distribution capability.
3Adaptability or versatility
If delay units with different characteristics are used to achieve various delay settings, then delay range is increased, but delay increment variation increases leading to nonlinear behavior
Solution Approach 1:
The time delay circuit is segmented into multiple identical delay units, each contributing a fixed time delay increment. The total delay is achieved by selectively enabling different numbers of these segmented units through the one-hot decoder. This segmentation ensures that each unit contributes equally to the delay, maintaining uniform delay increments across the entire delay range while providing adaptability through combinatorial selection.
Data Source
AI summary
Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.