Capacitive-Coupled Level Shifter with Symmetric Divider Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifter designs for high-speed gate driver applications face challenges in achieving high common mode rejection, speed performance, and minimizing layout area, especially when dealing with high voltage domains that exceed the breakdown capability of available components.
Innovation Solution
A capacitive-coupled level shifter design that includes a capacitive divider circuit and a comparator circuit, with a resistor ladder for DC biasing, and a speed booster circuit to enhance gain, which cancels out common mode voltage and translates static control signals into continuous sequences of pulses to prevent false triggering due to noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If cascoding approach is used to implement high voltage level shifter, then voltage handling capability is improved, but speed performance deteriorates and layout area increases
Solution Approach 1:
The patent introduces a bootstrap capacitor as an intermediary energy storage element that couples the low-voltage control signal to the high-voltage gate driver. This capacitor acts as a mediator that transfers voltage potential without requiring direct high-voltage signal paths, thereby avoiding the speed degradation associated with cascaded high-voltage devices while maintaining the necessary voltage handling capability.
Solution Approach 2:
The patent employs periodic charging and discharging of the bootstrap capacitor to dynamically transfer voltage levels. The control signal is periodically refreshed through the bootstrap network, allowing the gate driver to maintain high-voltage operation capability while using low-voltage control logic. This periodic action enables voltage level shifting without the speed penalties of static cascoded structures.
2Strength
If cascoding approach is used to implement high voltage level shifter, then voltage handling capability is improved, but layout area increases
Solution Approach 1:
The bootstrap capacitor serves as a compact intermediary that enables high-voltage gate driving from low-voltage control signals. By using this single energy storage element rather than multiple cascaded high-voltage devices, the layout area is significantly reduced while maintaining the ability to handle high voltages through dynamic voltage transfer.
Solution Approach 2:
The patent uses the bootstrap capacitor to copy or replicate the low-voltage control signal at a higher voltage level. Instead of physically cascading multiple high-voltage devices, the capacitor creates a voltage-copied version of the control signal that drives the high-voltage gate, thereby achieving the same functional result with minimal layout area.
3Device complexity
If static control input signal is used, then circuit simplicity is improved, but reliability deteriorates due to false triggering from noise
Solution Approach 1:
The patent transforms the static control input signal into a periodic sequence of pulses through the bootstrap capacitor charging and discharging cycles. This periodic refreshing of the control signal prevents noise accumulation and false triggering, as the continuous periodic action actively re-establishes the valid logic state, thereby improving reliability without significantly increasing circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive-coupled level shifter achieves higher speed performance, reduced dependency on temperature and process variations, and occupies less chip area, ensuring reliable operation in high-speed and high-power applications with improved common mode rejection and power supply rejection ratio.
Implementation Method 1
a capacitive divider circuit (204) capacitively coupling the input terminals (INP, INN) to the input terminals (A, B) of the comparator circuit (202)
Data Source
AI summary
A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.