Symmetric H-Tree Clock Distribution with Routing Blockage Handling
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Solution Overview
Problem
Constructing a symmetric clock-distribution tree in high-performance integrated circuits (ICs) is challenging due to unevenly distributed clock sinks, routing blockages, and power grid interference, leading to non-symmetric and high-skew clock distribution trees that are inefficient for high-performance applications.
Innovation Solution
A computer-implemented method and system that identify alternate locations for clock-tree segments to route clock-signal wires symmetrically, using a combination of bottom-up and top-down processes to maintain symmetry and avoid routing blockages, while updating location information and constructing hierarchical clock-tree segments to ensure minimal clock-skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods place the entire clock-tree structure centered around the middle portion of the IC, then the construction process is simple, but the resulting clock distribution tree is non-symmetric and has high clock-skew
Solution Approach 1:
The clock distribution tree is divided into multiple clock-tree segments that are constructed hierarchically from bottom-up. Each segment is paired and wired to form larger segments, allowing symmetric construction while accommodating routing blockages by adjusting individual segment locations rather than the entire tree structure.
Solution Approach 2:
The patent introduces hierarchical levels (bottom-up construction) and alternate location selection in routing space to resolve symmetry issues. By operating in the dimension of hierarchical segmentation and alternative routing paths, the method achieves symmetric clock distribution even when direct routing is blocked.
2Adaptability or versatility
If routing tracks are unavailable due to routing blockages and power grid interference, then conventional methods route wires around blockages with unique paths, but this results in high clock-skew and non-symmetric distribution
Solution Approach 1:
The patent intentionally allows asymmetric routing paths at the segment level to accommodate blockages, but uses symmetric pairing of segments to achieve overall symmetry. Individual segments may have different routes, but paired segments are configured to maintain equal wirelength from the clock source, converting local asymmetry into global symmetry.
Solution Approach 2:
Different regions of the clock distribution tree are treated with different routing strategies based on local blockage patterns. Each clock-tree segment pair is optimized independently for its local routing environment, allowing adaptive routing decisions that maintain symmetry while navigating local obstacles.
3Adaptability or versatility
If higher layers of the IC are used for clock-tree distribution, then routing flexibility is improved, but the larger surface area required occupies more space unavailable due to component placement
Solution Approach 1:
By segmenting the clock distribution into hierarchical levels, the patent can use higher routing layers selectively for specific segment connections rather than the entire tree. This reduces the total surface area occupied on higher layers while maintaining routing flexibility where needed.
Solution Approach 2:
The patent transitions between different routing layers (vertical dimension) and horizontal routing tracks (horizontal dimension) to optimize space usage. By alternating between layers and using alternate locations, the design achieves routing flexibility without permanently occupying large areas on any single layer.
Data Source
AI summary
Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.