Symmetric Interconnect Layout for Rotation-Tolerant Chip Stacking
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Solution Overview
Problem
Bonding errors occur during the stacking of semiconductor chips due to inadvertent rotation, leading to incorrect connections between interconnects that transmit and receive data signals, resulting in communication errors.
Innovation Solution
Symmetrically arranging interconnects on the semiconductor chips to ensure correct bonding regardless of rotational orientation, using quadrants and symmetrical patterns to align and connect interconnects accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If asymmetric interconnect arrangement is used, then manufacturing precision can be improved through precise alignment, but bonding errors occur due to inadvertent rotation during stacking
Solution Approach 1:
The patent applies asymmetry in reverse by deliberately creating symmetric interconnect arrangements where interconnects in different zones are mirror images or identical patterns. This symmetry ensures that even if the chip rotates during bonding, the interconnects will still align correctly with the corresponding interconnects on the opposing chip, eliminating bonding errors caused by rotational misalignment while maintaining manufacturing precision
2Reliability
If symmetric interconnect arrangement is used, then bonding errors due to rotation are reduced, but interconnect density and signal routing flexibility may be limited
Solution Approach 1:
The patent segments the chip surface into multiple zones (first, second, third, and fourth zones) with interconnects arranged in specific patterns within each zone. By dividing the interconnect array into segmented zones with symmetric relationships between them, the design maintains rotational tolerance while preserving routing flexibility through the structured organization of different signal types in different zones
3Productivity
If conventional bonding processes are used, then manufacturing speed can be maintained, but bonding errors lead to reduced manufacturing yield
Solution Approach 1:
The symmetric interconnect arrangement is established during the interconnect formation process before chip stacking. This preliminary design feature built into the chip structure proactively prevents bonding errors from occurring during the stacking process, eliminating the need for slower, more precise alignment processes while maintaining high manufacturing yield through inherent rotational tolerance
Data Source
AI summary
A system includes a semiconductor chip and a plurality of interconnects. The semiconductor chip has a bottom or top surface divided into two or more zones. The interconnects are formed over the zones. The interconnects in each zone are arranged in an array of rows. Each interconnect in a first zone is connected to a respective first interconnect in a fourth zone. The interconnects from top to bottom rows in the first zone are symmetric with the interconnects from bottom to top rows in the fourth zone about the y-axis. Each interconnect in a second zone is connected to a respective interconnect in a third zone. The interconnects from top to bottom rows in the second zone are symmetric with the interconnects from bottom to top rows in the third zone about the y-axis.