Symmetric Leaf Node Swapping for PLD Interconnect Delay Reduction
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Solution Overview
Problem
Modern programmable logic devices (PLDs) face increased interconnect delays, which dominate over logic delays, hindering operational speed and efficiency, as complexity grows and sub-micron technology advances.
Innovation Solution
A computer-implemented method that identifies timing critical wires and determines fanout free cones within the circuit design, allowing for the swapping of symmetric leaf nodes to reduce delays, while maintaining functionality, by selectively swapping signals based on delay reduction analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If interconnect delays are reduced through traditional placement optimization, then timing performance improves, but device complexity and optimization difficulty increase due to the dominant interconnect nature of modern PLDs
Solution Approach 1:
The patent applies asymmetry by breaking the symmetry of equivalent leaf nodes in the circuit design. By identifying and swapping only the critical leaf node with non-critical ones, rather than treating all leaf nodes equally, the method creates an asymmetric optimization approach that targets specific timing-critical paths while leaving other equivalent nodes unchanged, thereby reducing interconnect delay without requiring comprehensive re-optimization of the entire complex device.
Solution Approach 2:
The patent implements local quality by focusing optimization efforts on specific local regions of the circuit design - namely, the fanout-free cones containing critical leaf nodes. Rather than applying global placement optimization across the entire PLD, the method identifies and optimizes only the local sub-circuits (FFCs) that contain timing-critical wires, allowing for targeted delay reduction in specific areas while maintaining the overall device structure.
2Loss of time
If comprehensive signal swapping is performed to reduce interconnect delays, then timing performance improves, but computational complexity and processing time increase
Solution Approach 1:
The patent extracts and isolates the critical elements from the entire circuit design by identifying critical leaf nodes and their associated fanout-free cones. By separating the optimization problem into discrete, manageable FFCs containing only critical paths, rather than attempting to optimize the entire circuit simultaneously, the method reduces computational complexity while maintaining effectiveness in reducing timing delays.
Solution Approach 2:
The patent segments the circuit design into multiple fanout-free cones (FFCs), each containing a critical leaf node and its associated logic. By dividing the optimization problem into these independent segments, the method allows for parallel processing and reduces the overall computational burden compared to optimizing the entire circuit as a single unit, thereby improving optimization efficiency while achieving timing improvement.
3Loss of time
If leaf nodes are swapped to reduce critical wire delays, then interconnect delay decreases, but circuit functionality may be altered
Solution Approach 1:
The patent applies inversion by reversing the conventional approach: instead of modifying the critical leaf node's connections to reduce delay, it swaps the critical leaf node with equivalent non-critical leaf nodes. This inverse approach maintains circuit functionality because equivalent nodes produce identical outputs, while the critical node's signal is rerouted through a shorter path, thereby reducing delay without altering functional behavior.
Solution Approach 2:
The patent changes the physical parameter (position/connection) of the critical leaf node while maintaining the functional parameter (logic equivalence) constant. By swapping the critical node with equivalent nodes that have different physical locations or connection characteristics, the method alters the interconnect delay parameter while preserving the functional equivalence of the circuit, ensuring reliability is maintained.
Data Source
AI summary
A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.