Symmetric Memory Array Layout for Predictable Access Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory arrays with multiple banks experience unpredictable and unacceptably long access times due to asymmetric access timing, particularly when accessing remote banks, leading to reduced overall memory speed.
Innovation Solution
Implementing a memory array design with symmetric access timing by coupling memory banks in a manner that balances input and output signal paths, ensuring that control and data signals traverse between groups of memory banks in a uniform and predictable manner, thereby reducing worst-case access scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory banks are arranged in a conventional asymmetric layout, then the memory array can be compact and area-efficient, but access time becomes unpredictable and unacceptably long when accessing remote banks
Solution Approach 1:
The patent applies asymmetry in reverse - it creates a symmetric memory bank arrangement where banks are positioned equidistantly from input and output circuitry. This symmetry ensures that signal path lengths are equalized, eliminating the access time variations that occur in asymmetric layouts when accessing remote banks versus nearby banks.
Solution Approach 2:
The patent creates equipotential signal paths by arranging memory banks symmetrically around the input and output circuitry. This ensures that all memory banks are at equal electrical distance from the control and data signal sources, eliminating timing skew and access time variations across different banks.
2Speed
If memory banks are positioned close to input/output circuitry, then access time is fast, but the memory array area increases significantly
Solution Approach 1:
The patent transitions from a linear or one-dimensional memory bank arrangement to a two-dimensional symmetric layout. By organizing banks around the input/output circuitry in a radial or distributed pattern, the design achieves both compact area utilization and equalized signal path lengths, preventing area expansion while maintaining fast access times.
3Device complexity
If asymmetric access timing is used in memory banks, then device complexity is reduced, but overall memory performance decreases due to worst-case timing constraints
Solution Approach 1:
The patent changes the geometric parameter of memory bank positioning from asymmetric to symmetric arrangement. This physical parameter change equalizes signal propagation delays across all banks, allowing the memory system to operate at higher speeds without requiring complex timing compensation circuitry, thus improving performance while maintaining manageable complexity.
Data Source
AI summary
A memory device includes a bitcell array having at least a first plurality of first adjacent bitcell banks and a second plurality of second adjacent bitcell banks. One or more bitcell array input lines are coupled to the bitcell array at a first physical location between the first adjacent bitcell banks. One or more bitcell array output lines are coupled to the bitcell array at a second physical location between the second adjacent bitcell banks. The one or more bitcell array input lines are further coupled from the first plurality of adjacent bitcell banks to the second plurality of bitcell banks at a physical location between the second plurality of adjacent bitcell banks. The one or more bitcell array output lines are further coupled from the second plurality of bitcell banks to the first plurality of bitcell banks at a physical location between the first plurality of bitcell banks.