Symmetric Memory Portion Error Capture Logic
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Solution Overview
Problem
Existing built-in self tests (BISTs) for integrated circuit memory are process intensive and may fail to capture all memory failures due to counter size limitations, leading to inconsistent error capture and difficulty in identifying memory addresses during high-speed tests.
Innovation Solution
The memory is separated into symmetric portions, where one portion is used for testing and the other for capturing errors, with error data stored at identical locations in both portions, allowing for efficient error mapping and reduced test time by swapping roles after the test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a typical BIST runs through the entire memory repeatedly to capture errors, then error capture completeness may improve, but test time increases significantly and counter size limitations prevent capturing all failures
Solution Approach 1:
The memory is divided into two symmetric portions: a first memory portion used for testing and a second memory portion used for capturing errors. This segmentation allows the test to run through the memory once without repeated iterations, as errors are captured in the second portion while the first portion is being tested, thereby reducing test time while maintaining error capture completeness.
Solution Approach 2:
The second memory portion acts as an intermediary capture memory that receives and stores error data from the first memory portion during the test. This intermediary structure allows error information to be captured without interrupting the test flow or requiring counter limitations, enabling complete error capture in a single test pass.
2Measurement precision
If memory addresses are identified during BIST with complicated scrambling of address lines, then error location precision improves, but device complexity and difficulty of detecting errors increase
Solution Approach 1:
The patent creates a copy of the address information by storing error data at the same address location in the second memory portion where the error occurred in the first memory portion. This copying approach preserves the exact address information without requiring complex address line scrambling or additional address identification logic, thereby reducing device complexity while maintaining error location precision.
3Measurement precision
If the test is stopped at every error to dump error data (SONE test), then error capture accuracy improves, but productivity decreases due to repeated test runs
Solution Approach 1:
The test continues without interruption by capturing errors in the second memory portion while the first memory portion is being tested. This continuous operation eliminates the need to stop the test at every error to dump data, thereby maintaining error capture accuracy while significantly improving test efficiency and productivity.
Solution Approach 2:
The second memory portion is pre-configured as a capture memory with the same structure as the first memory portion, allowing error data to be stored immediately at the correct address location without requiring post-test processing or repeated test runs to capture all errors.
Data Source
AI summary
A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memory portion. Error logic output from the first memory portion is captured (stored) in the second memory portion during the BIST run process. Error logic output from the first memory portion may include error data and an address of the memory error in the first memory portion. As the first and second memory portions are symmetric, the memory errors captured (stored) in the second memory portion are located at identical locations to the location of the memory errors in the first memory portion. A memory dump from the second memory portion after the BIST may provide a map of the memory errors in the first memory portion.