Symmetric Hardware Peripheral Management for CPU-BMC Resilience

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Solution Overview

Problem

Network devices lack a flexible and resilient system for managing hardware peripherals, as existing configurations often require different management systems and lack redundancy, leading to inefficiencies and potential service disruptions.

Innovation Solution

A network device with a Central Processing Unit (CPU) and Baseboard Management Controller (BMC) that synchronize and manage hardware peripherals through a symmetric interface, allowing both to independently control and update peripheral states while maintaining synchronized local databases, enabling flexibility and redundancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single management system is used to control hardware peripherals, then device complexity is reduced, but reliability and resilience are worsened due to lack of redundancy

Engineering Contradiction:
ImproveresilienceVSAvoidcontrol system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control function is segmented into two independent management systems (first management system via CPU and second management system via BMC), each capable of independently controlling hardware peripherals. This segmentation enables redundancy and resilience while maintaining manageable complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each management system maintains its own local database of peripheral states, allowing independent operation and data storage. This local quality approach enables each controller to function autonomously, improving reliability without requiring a centralized complex system.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If both CPU and BMC independently control hardware peripherals, then adaptability and flexibility are improved, but synchronization complexity and data consistency challenges worsen

Engineering Contradiction:
Improvemanagement flexibilityVSAvoidsynchronization complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms where each management system notifies the other of state changes to hardware peripherals. This feedback loop ensures both controllers have updated information about peripheral states, enabling coordinated control while maintaining independence and flexibility.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Both management systems are given equal status and capability to control any hardware peripheral. This equipotentiality approach ensures neither controller is subordinate to the other, allowing flexible management strategies while maintaining symmetric rights and responsibilities.

Inventive Principle:
Principle #12Equipotentiality

3Productivity

If separate data structures are maintained by CPU and BMC, then data independence and processing efficiency are improved, but information consistency and coordination are worsened

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddata consistency
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

Each management system maintains its own local database for peripheral states, enabling independent processing and improved efficiency. The feedback mechanism ensures both databases remain consistent by notifying the other controller of state changes, preventing information loss while maintaining processing independence.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250321902A1Symmetrical Control of Hardware Peripherals
Publication Date: 2025.10.16 MELLANOX TECHNOLOGIES LTD(IL)
  • US20250321902A1 patent drawing

AI summary

A network device includes packet processing circuitry, one or more hardware peripherals, a Baseboard Management Controller (BMC) and a Central Processing Unit (CPU). The packet processing circuitry is to communicate packets over a network. The BMC is to control the hardware peripherals. The CPU is to perform control-plane operations for communicating the packets by the packet processing circuitry. Each of the CPU and the BMC is to modify states of the hardware peripherals, and to synchronize the other of the BMC and the CPU with the modified state of the hardware peripherals.