Symmetric Phase Interpolator for Accurate Multi-Phase Clock Generation
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Solution Overview
Problem
Conventional CDR circuits face challenges in accurately generating multiple phases of a periodic signal, particularly intermediate degree increments, due to limitations in conventional phase detectors and voltage-controlled oscillators, which are asymmetric and unable to compensate for built-in phase offsets.
Innovation Solution
A CDR circuit incorporating a phase interpolator integrated with a symmetric phase detector, utilizing parallel cross-coupled Gilbert cells to generate multiple clock phases, including 8-phase signals for quarter-rate architectures, and employing a phase interpolator block to adjust decision phases, reducing the burden on the voltage-controlled oscillator and improving phase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional phase detectors and voltage-controlled oscillators are used to generate multiple clock phases, then the circuit implementation is straightforward, but the phase accuracy for intermediate degree increments deteriorates
Solution Approach 1:
The phase detection function is segmented into multiple parallel cross-coupled Gilbert cells, each handling a specific phase comparison. This segmentation allows the system to accurately detect multiple intermediate phase increments (e.g., 22.5°, 45°, 67.5°) by distributing the detection task across multiple specialized units, thereby improving phase accuracy while maintaining circuit simplicity.
Solution Approach 2:
A symmetric phase detector is introduced as an intermediary component between the voltage-controlled oscillator and the phase interpolator. This symmetric phase detector compensates for built-in phase offsets and provides accurate phase error signals for intermediate phases, enabling precise clock phase generation without complicating the overall circuit architecture.
2Device complexity
If conventional asymmetric phase detectors are used, then the circuit design is simple, but the built-in phase offset cannot be compensated
Solution Approach 1:
The patent employs symmetric phase detector design where cross-coupled Gilbert cells are arranged to provide symmetry in the phase detection process. This symmetry ensures that phase offsets are equally detected in both directions, allowing for accurate compensation of built-in phase offsets without significantly increasing detector design complexity.
Solution Approach 2:
The symmetric phase detector provides feedback signals that include information about built-in phase offsets. This feedback is used by the control logic to adjust and compensate for the offsets, thereby improving phase offset accuracy while maintaining relatively simple detector design through the use of standard Gilbert cell structures.
3Device complexity
If conventional phase detectors with flip-flops are used, then the circuit structure is straightforward, but the detection speed is limited
Solution Approach 1:
The patent replaces the mechanical flip-flop-based phase detection mechanism with a Gilbert cell-based mixer structure. The Gilbert cell uses transistor switching and current steering to achieve phase detection, eliminating the speed limitations of flip-flops while maintaining a relatively straightforward circuit structure based on standard CMOS transistor configurations.
Solution Approach 2:
The cross-coupled Gilbert cells operate in a periodic manner, with each cell processing phase comparisons at optimized timing intervals. This periodic operation allows the detector to achieve high speeds by concentrating detection activity in specific time windows, thereby improving detection speed while keeping the overall circuit structure simple and manageable.
4Device complexity
If voltage-controlled oscillator generates all clock phases, then the system architecture is simple, but the bandwidth requirements become stringent
Solution Approach 1:
The clock phase generation function is segmented between the voltage-controlled oscillator and phase interpolators. The VCO generates a base clock signal, and multiple phase interpolators distribute and phase-shift this signal to create the required multiple clock phases. This segmentation relaxes the bandwidth requirements on the VCO while maintaining simple system architecture.
Solution Approach 2:
Phase interpolators are introduced as intermediary components between the VCO and the various functional blocks requiring clock phases. These interpolators take the VCO output and generate multiple phase-shifted versions, thereby reducing the bandwidth burden on the VCO while keeping the overall system architecture simple and modular.
Data Source
AI summary
In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.