Symmetric QS Vector Generation for Turbo Interleaver Addresses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The generation of vectors for Turbo Codes using discrete power series with symmetry is time-consuming and memory-intensive, particularly due to the need for calculating and storing multiple QSvectors in Turbo Interleavers, which complicates the process of generating interleave read addresses.
Innovation Solution
An interleaver with a read address generator that utilizes a vector generator for a discrete power series symmetric about a term, allowing the second portion of the vectors to be generated using symmetry, thereby reducing computational effort and memory requirements by only computing and storing the first half of the vector series, with the second half derived from the first half using symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple QSvectors are generated and stored for Turbo Interleavers, then the accuracy and completeness of interleave read address generation is improved, but the memory consumption and computational time increase substantially
Solution Approach 1:
The discrete power series is divided into two symmetric portions. Instead of generating and storing all QSvectors, the patent generates only the first portion and uses symmetry properties to derive the second portion, effectively segmenting the computational task and reducing memory requirements by half while maintaining complete accuracy for interleave read address generation.
Solution Approach 2:
The patent pre-establishes the symmetry relationship of the discrete power series beforehand. By identifying and storing only the first portion of the series with known symmetry properties, the system prepares sufficient information in advance to reconstruct the complete series when needed, eliminating the need to store all QSvectors while ensuring accurate interleave read address generation.
2Measurement precision
If multiple locations in QSvectors are computed for multi-channel Turbo Interleaver, then the completeness of interleave read addresses is improved, but the computational time increases due to pseudo-random nature of discrete power series
Solution Approach 1:
The patent segments the computational workload by dividing the discrete power series into two portions. For multi-channel Turbo Interleaver, only the first portion needs to be computed directly, while the second portion is derived using symmetry. This segmentation reduces the number of direct computations required, significantly decreasing computational time while ensuring all necessary interleave read addresses for multiple channels are obtained.
Solution Approach 2:
Instead of computing multiple locations in pseudo-random QSvectors independently, the patent creates the second portion as a symmetric copy/derivation from the first portion. This copying approach leverages the inherent symmetry of the discrete power series, allowing rapid generation of complete QSvectors for multiple channels without repeating the full computational process, thus reducing computational time while maintaining completeness.
Data Source
AI summary
Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.