Symmetric Via Layout for 3D Memory Chip Signal Integrity
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges with high parasitic capacitance and parasitic resistance in chip connections, affecting signal transmission quality, and face-to-face stacking methods are complex and costly.
Innovation Solution
A chip-stacked structure with symmetric conductive via groups transmitting global signals and channel signals, allowing for face-to-face stacking with reduced parasitic capacitance and resistance, and incorporating global signal switching and redundancy mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked through bonding process to form three-dimensional semiconductor device, then storage electron density and manufacturing cost per memory cell are improved, but parasitic capacitance and parasitic resistance in connection structures increase
Solution Approach 1:
The connection structure is segmented into multiple conductive via groups, where each group contains multiple conductive vias that are symmetrically distributed. This segmentation allows the signal transmission function to be distributed across multiple parallel paths, reducing the parasitic capacitance and resistance of individual connection paths while maintaining high storage density through the stacked architecture.
Solution Approach 2:
The patent employs symmetric distribution of conductive vias within each via group relative to the center point of the active surface. This symmetric (rather than asymmetric) arrangement ensures balanced electrical characteristics and minimizes parasitic effects by equalizing the distribution of capacitive and resistive elements around the signal path.
2Productivity
If face-to-face stacking method is used to stack multiple chips, then three-dimensional semiconductor device is formed, but process complexity and manufacturing cost increase
Solution Approach 1:
The conductive via groups with symmetric distribution are designed to serve multiple functions: they provide signal transmission, reduce parasitic effects, and enable alignment between stacked chips. The same via group structure handles both global signals and channel signals, simplifying the overall design and reducing process complexity compared to dedicated separate structures for each function.
Solution Approach 2:
The patent transitions from two-dimensional planar connections to three-dimensional vertical stacking with conductive vias extending through the chip thickness. This dimensional change enables higher storage density by utilizing the vertical dimension for stacking multiple memory chips, while the symmetric via groups maintain signal integrity in this three-dimensional configuration.
Data Source
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AI summary
Embodiments of the present disclosure provide a memory chip, a logic chip, a chip-stacked structure, and a memory. A global signal region of the memory chip is penetrated by multiple conductive via groups, and each conductive via group includes a first dummy conductive via group and a second dummy conductive via group. The first dummy conductive via group includes a first conductive via and a fourth conductive via, and the second dummy conductive via group includes a second conductive via and a third conductive via. The first dummy conductive via group is configured to transmit the same first global signal, and the second dummy conductive via group is configured to transmit the same second global signal.