Rotationally Symmetric Vias for IC Die Stack Signal Integrity
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Solution Overview
Problem
As the number of integrated circuit dies stacked increases, existing technologies face challenges in maintaining signal quality and bus speeds due to increased loading on signal buses, which degrades performance.
Innovation Solution
The implementation of an integrated circuit die stack with rotationally symmetric pass-through vias (PTVs) and through-silicon vias (TSVs) allows for efficient signal line connection between dies, reducing bus signal loads and enhancing signal quality and speed by aligning PTVs and TSVs on each die for optimal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple integrated circuit dies are stacked to increase storage capacity and performance, then the functionality and data capacity are improved, but the signal quality and bus speeds deteriorate due to increased loading on signal buses
Solution Approach 1:
The patent divides the signal transmission path into separate dedicated pathways for each die by rotating alternating dies by 45 degrees. This segmentation prevents signal lines from multiple dies from sharing the same bus, thereby reducing loading effects and maintaining signal quality as more dies are stacked.
Solution Approach 2:
The patent introduces rotational asymmetry (45-degree rotation) between alternating dies in the stack. This asymmetric arrangement causes the via positions to misalign, preventing direct overlap of signal lines from different dies and reducing electromagnetic interference and loading on shared buses.
2Quantity of substance
If multiple integrated circuit dies are stacked to increase storage capacity, then the data capacity is improved, but the bus speeds deteriorate due to increased loading on signal buses
Solution Approach 1:
The patent segments the bus architecture into die-specific pathways through rotational offset. Each die's signal lines travel through dedicated via positions that do not overlap with adjacent dies, reducing congestion and maintaining high bus speeds even as the number of stacked dies increases.
Solution Approach 2:
By rotating alternating dies by 45 degrees, the patent creates an asymmetric via arrangement that eliminates signal line overlap. This reduces capacitive loading and resistive effects on the buses, thereby maintaining faster signal transmission speeds across the stack.
3Adaptability or versatility
If signal lines are wrapped outside the dies or redistribution layers are placed between dies to connect multiple dies, then the connectivity between dies is achieved, but the device complexity increases
Solution Approach 1:
Instead of routing signal lines externally around the dies or adding complex redistribution layers between dies, the patent inverts the approach by using vertical through-silicon vias that pass directly through each die. The connectivity is achieved through the substrate and vias rather than through complex inter-die routing structures.
Solution Approach 2:
The patent transitions from two-dimensional planar routing (signal lines wrapped outside dies or redistribution layers between dies) to a three-dimensional vertical architecture using through-silicon vias. This dimensional change simplifies the interconnect structure by utilizing the vertical stacking dimension for signal transmission.
Data Source
AI summary
An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.


