Symmetrical Die Layout for Higher-Capacity Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packages face challenges in increasing capacity and performance without increasing height or trace length, leading to issues with signal and power integrity.
Innovation Solution
Semiconductor dies are fabricated with symmetrical circuit layouts using symmetrical wafer masks, allowing for adjacent placement on a PCB with reduced trace lengths and improved die pad alignment, thereby enhancing capacity and integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional memory dies are added to a stack of memory dies to increase capacity, then the capacity of the non-volatile memory device is improved, but the height of the semiconductor package increases
Solution Approach 1:
The patent transitions from vertical stacking (increasing height in the Z-dimension) to lateral placement (increasing capacity in the X-Y plane). Multiple memory dies are arranged side-by-side on the same substrate rather than stacked vertically, thereby increasing storage capacity without increasing package height.
2Quantity of substance
If additional memory dies are added to a stack of memory dies to increase capacity, then the capacity of the non-volatile memory device is improved, but the risk of bond wires becoming crossed or overlapping increases
Solution Approach 1:
The patent extracts the bonding function from traditional wire bonding to a different interconnection approach. By using direct pad-to-pad connections or alternative interconnect structures on the substrate, the patent eliminates bond wires entirely, thereby removing the risk of wire crossing and overlapping while accommodating multiple memory dies.
3Quantity of substance
If a second stack of memory dies is added next to a first stack to increase capacity, then the capacity of the non-volatile memory device is improved, but the length of traces that communicatively couple the second stack increases
Solution Approach 1:
The patent merges the interconnection structure by placing both memory die stacks on a common substrate with shared trace routing. The substrate acts as a unified interconnect platform, allowing traces to efficiently route to both stacks without requiring excessively long individual trace lengths, thereby maintaining signal integrity while increasing capacity.
4Quantity of substance
If a second stack of memory dies is added next to a first stack to increase capacity, then the capacity of the non-volatile memory device is improved, but the desired signal and/or power integrity requirements may not be achievable
Solution Approach 1:
The patent applies local quality by optimizing the substrate design with region-specific trace routing, impedance control, and signal integrity features tailored to each memory die stack's location. This localized optimization ensures that signal and power integrity requirements are met for each stack while accommodating increased capacity through multiple dies.
Data Source
AI summary
A semiconductor package includes a first stack of semiconductor dies having a first circuitry layout and a second stack of semiconductor dies having a second circuitry layout. The second circuitry layout is symmetrical to the first circuitry layout. The symmetrical circuitry layout enables the second stack of semiconductor dies to be positioned on a PCB adjacent to the first stack of semiconductor dies. Additionally, the symmetrical circuitry layout enables die pads on the first stack of semiconductor dies to be adjacent to die pads on the second stack of semiconductor dies. Contacts on the PCB are provided between the first stack of semiconductor dies and the second stack of semiconductor dies. Bond wires electrically couple the die pads of the first stack of semiconductor dies to a first subset of contacts and electrically couple the die pads of the second stack of semiconductor dies to a second subset of contacts.