Symmetrical Embedded Passive Substrate Warpage Reduction
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Solution Overview
Problem
Conventional embedded passive substrates (EPS) suffer from uneven heat management, warpage, and electrical noise issues due to multiple metal and insulating layers, leading to inefficiencies in high-frequency applications like RF wireless communications.
Innovation Solution
A symmetrical three-layer embedded passive substrate structure is developed, where the second metal layer is formed between stacked insulating layers, reducing signal loop length and eliminating additional material between insulating and conductive layers, thereby enhancing heat management and reducing electrical noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metal and insulating layers are used in conventional EPS, then electrical connectivity is achieved, but heat management becomes uneven and warpage occurs
Solution Approach 1:
The patent applies asymmetry by removing the bottom metal layer and using a single top metal layer, creating an asymmetric structure that eliminates warpage while maintaining electrical connectivity. This asymmetric design balances the substrate structure and prevents the warpage issues caused by symmetric multi-layer configurations.
Solution Approach 2:
The patent extracts and removes unnecessary components, specifically eliminating the bottom metal layer and additional insulating layers. This extraction simplifies the structure to only the essential top metal layer, reducing complexity while maintaining functionality and improving heat management.
2Reliability
If multiple metal and insulating layers are used in conventional EPS, then electrical connectivity is achieved, but electrical noise increases
Solution Approach 1:
The patent extracts and removes unnecessary metal and insulating layers, keeping only the essential top metal layer. This extraction eliminates potential sources of electrical noise from multiple layers while maintaining the required electrical connectivity through the simplified single-layer structure.
3Strength
If additional material is used between insulating and conductive layers, then structural support is provided, but signal loop length increases
Solution Approach 1:
The patent extracts and eliminates additional material between insulating and conductive layers, using only the essential substrate structure. This removal shortens the signal loop length while the substrate itself provides the necessary structural support, eliminating the need for extra material layers.
4Reliability
If multiple layers are used in conventional EPS, then electrical functionality is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes unnecessary metal and insulating layers, simplifying the multi-layer structure to a single top metal layer. This extraction reduces manufacturing complexity by eliminating multiple deposition and patterning steps while maintaining essential electrical functionality.
Solution Approach 2:
The patent segments the structure by separating the essential top metal layer from unnecessary bottom layers, keeping only the functional components. This segmentation simplifies the overall structure to its essential segments, reducing manufacturing complexity while preserving electrical functionality.
Data Source
AI summary
A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.