Symmetrical Laminate for White Bump Sensitivity Testing
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Solution Overview
Problem
Conventional organic laminates in chip bonding exhibit warpage and coefficient of thermal expansion (CTE) mismatch with silicon chips, leading to thermally-induced stress and failure of BEOL structures, known as white bumps, which are difficult to distinguish from warpage effects, hindering the implementation of lead-free bump technology.
Innovation Solution
A symmetrical, flat laminate structure is designed with balanced conductive and insulating layers to minimize warpage and isolate CTE mismatch effects, allowing for independent evaluation of white bump sensitivity and optimization of laminate design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional organic laminates are used for chip assembly, then cost-effective packaging with better electrical performance is achieved, but warpage occurs leading to cracking or delamination of BEOL structures (white bumps)
Solution Approach 1:
The patent applies asymmetry principle by creating a symmetrical test structure where identical layers are placed on opposite sides of the core laminate. This symmetrical configuration cancels out warpage effects that normally occur in conventional asymmetrical laminates, allowing isolation and measurement of CTE mismatch effects without the confounding variable of warpage-induced stress.
Solution Approach 2:
The patent segments the laminate into distinct functional layers: a core laminate material and balanced layers of conductive and insulating materials on opposite sides. This segmentation allows independent evaluation of each layer's contribution to thermal expansion and mechanical stress, enabling precise measurement of CTE mismatch effects.
2Ease of operation
If asymmetrical laminate structures are used, then conventional chip bonding is achieved, but warpage and CTE mismatch effects are coupled making it difficult to determine the cause of white bumps
Solution Approach 1:
The patent extracts the warpage variable from the test structure by using symmetrical layer configuration, separating it from the CTE mismatch effects. This extraction allows independent measurement of white bump sensitivity to CTE mismatch without the confounding influence of warpage, enabling precise determination of causal relationships.
3Ease of manufacture
If lead-free bump metallurgy is used, then cost reduction is achieved, but stiffer bumps create higher thermally-induced stress resulting in increased white bump formation
Solution Approach 1:
The patent changes the material parameters of the test structure by using balanced layers with specific thermal and mechanical properties that simulate lead-free bump conditions. This allows evaluation of white bump sensitivity under controlled parameters that match lead-free bump metallurgy characteristics without the variability of conventional processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The symmetrical laminate structure reduces warpage-related issues, enabling faster and cheaper evaluation of white bump sensitivity and CTE mismatch contributions, facilitating the development of lead-free bump technology and improving chip bonding reliability.
Implementation Method 1
The coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic laminate creates thermally-induced stress/strain in the flip-chip structure during the chip assembly process
Implementation Method 2
there are stresses produced during cool-down of the modules from the chip join temperature
Data Source
AI summary
A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.