Symmetrical Memory Cell Structure for Chip Area Reduction
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory arrays require significant chip area due to the need for isolation structures between memory cells, which limits efficient use of space and increases manufacturing complexity.
Innovation Solution
The memory array design incorporates a memory cell structure with a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor, where memory cells in the same column share the same active area, reducing the need for isolation structures and allowing for smaller chip area without compromising driving ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation structures are added between memory cells for manufacturing stability, then manufacturing reliability is improved, but chip area increases significantly
Solution Approach 1:
Multiple memory cells (first memory cell and second memory cell) are merged into a single active area, sharing common structures such as the bit line, word line, and isolation structures. This consolidation reduces the total chip area while maintaining manufacturing stability through shared protective elements.
Solution Approach 2:
The isolation structure serves multiple functions: it isolates the first memory cell from the second memory cell, provides manufacturing stability for both cells simultaneously, and acts as a common boundary structure. This multi-functionality eliminates the need for separate isolation structures between adjacent memory cells.
2Reliability
If memory cells are disposed in different active areas, then manufacturing stability is improved, but chip area increases
Solution Approach 1:
The patent combines multiple memory cells into a single active area, allowing them to share common isolation structures and manufacturing processes. This merging approach maintains manufacturing stability while significantly reducing the total area occupied by multiple separate active areas.
3Reliability
If dummy isolation structures are added everywhere in the layout, then manufacturing process stability is improved, but chip area is largely increased
Solution Approach 1:
The patent extracts and eliminates redundant dummy isolation structures from the layout by implementing a design where memory cells share common isolation structures. This removal of unnecessary structures reduces chip area while maintaining the essential manufacturing process stability through the retained functional isolation structures.
Solution Approach 2:
The isolation structures in the patent serve universal functions for multiple memory cells simultaneously, eliminating the need for individual dummy isolation structures for each cell. This multi-functional approach maintains manufacturing process stability across the entire array while minimizing total isolation structure area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the chip area by up to 30% while maintaining the original driving ability, as memory cells in the same column can be disposed in the same active area, minimizing the use of isolation structures and optimizing space usage.
Implementation Method 1
When programming the memory cell 100, the antifuse transistor 130 is ruptured and behaves as a metal-oxide-semiconductor capacitor
Data Source
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AI summary
A memory array (20) having a small chip area includes a plurality of memory cells (2001,1 to 200M,N), each memory cell (2001,1) includes a first select transistor (210), a first following gate transistor (220), an antifuse transistor (230), a second following gate transistor (240), and a second select transistor (250). The second following gate transistor (240) and the second select transistor (250) are disposed symmetrically to the first following gate transistor (220) and the second select transistor (210) with respect to the antifuse transistor (230). With the two symmetrical paths provided by the two select gate transistors (210, 250) and the two following gate transistors (220, 240), the gate widths of transistors in the memory cell (2001,1) and the isolation structures between memory cells can be reduced, thereby reducing the chip area of the memory array (20).