Symmetrical Multi-Processor Serial Links for Endpoint Devices
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Solution Overview
Problem
Current virtualization technologies for peripheral devices in data centers often lead to performance jitter and increased latency due to the need for emulation software, which also ties up processor resources and does not efficiently utilize PCIe bus capabilities, especially when multiple processor devices communicate with a single endpoint device.
Innovation Solution
A computer system architecture that establishes symmetrical serial links between multiple processor devices and an endpoint device, allowing simultaneous communication and control without the need for PCIe Multi-Root I/O Virtualization, thereby reducing latency and improving performance by using a motherboard with individual serial link interfaces and expansion cards to couple processor devices directly to endpoint devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If emulation software is used to virtualize peripheral devices, then device sharing and isolation are improved, but processing capacity is consumed and performance jitter occurs
Solution Approach 1:
The patent extracts the emulation function from the host processor and relocates it to a dedicated endpoint device. The endpoint device independently emulates peripheral devices without requiring host processor intervention, thereby freeing up host processing capacity while maintaining device virtualization capabilities.
Solution Approach 2:
The patent introduces an endpoint device as an intermediary between the host processor and peripheral devices. This intermediary handles all emulation operations and I/O operations independently, preventing performance jitter from affecting the host processor while enabling efficient device sharing.
2Device complexity
If PCIe relay path is used to connect processor sockets to endpoint device, then physical connectivity is simplified, but latency and jitter increase
Solution Approach 1:
The patent segments the PCIe bus into multiple independent PCIe switches, each directly connected to processor sockets. This segmentation creates multiple direct paths from different processor sockets to the endpoint device, eliminating the need for relay routing and reducing latency and jitter.
3Ease of operation
If single processor socket is directly connected to endpoint device, then connection simplicity is improved, but communication efficiency between multiple processors deteriorates
Solution Approach 1:
The patent makes the endpoint device universally accessible to multiple processor sockets through the PCIe switch fabric. The endpoint device can simultaneously serve multiple processors with dedicated PCIe lanes, maintaining connection simplicity while enabling efficient multi-processor communication.
Data Source
AI summary
A computer system includes symmetrical sets of motherboard serial channels which couple processor devices on a motherboard with a common serial link interface. The common serial link interface can be coupled with an endpoint device to establish symmetrical serial links between the endpoint device and the processor devices. The computer system can include a riser card which can be coupled with the serial link interface. The riser card can include an endpoint device interface and serial channels which can couple the processor devices with the endpoint device via symmetrical limited selections of the motherboard serial channels. The riser can include additional interfaces which can couple the processor devices with additional expansion devices.