Symmetrical Network Interface for Processor Parallel Processing
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Solution Overview
Problem
Conventional processor architectures face inefficiencies in parallel processing due to asymmetrical interfaces, leading to high overhead in task management and communication between processor cores, which limits the full utilization of multiple processor cores and results in performance deterioration.
Innovation Solution
A processor with a symmetrical network interface that allows direct service requests between processor cores, enabling efficient parallel processing by using a service controller to manage and prioritize tasks, eliminating the need for child process generation overhead and interrupt pins, and allowing for immediate result handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an asymmetrical network interface is used in conventional processors, then the processor can maintain master control and compatibility with existing systems, but parallel processing efficiency deteriorates due to high overhead in task management and communication between processor cores
Solution Approach 1:
The patent applies asymmetry in reverse by implementing a symmetrical network interface where all processor cores have identical master and slave interfaces. This allows any core to initiate service requests (master) and respond to them (slave), eliminating the conventional asymmetrical architecture where only one processor could act as master. The symmetry enables efficient parallel processing by allowing direct core-to-core communication without operating system intervention.
2Productivity
If child processes are generated by the operating system for parallel processing, then task distribution is possible, but processing time increases due to overhead in allocating memory, copying information and data, and releasing memory
Solution Approach 1:
The patent extracts the task distribution function from the operating system and implements it directly in hardware at the processor core level. The service controller and symmetrical network interface enable cores to directly request and execute tasks on other cores without OS-generated child processes. This eliminates the overhead of memory allocation, data copying, and memory release associated with traditional child process management.
Solution Approach 2:
The service controller acts as an intermediary between processor cores, managing service requests and coordinating task execution directly between cores. This hardware-level mediator replaces the software-based OS child process mechanism, enabling efficient direct communication and task distribution without the overhead of process management.
3Productivity
If the operating system generates child processes for parallel processing requests, then task execution is possible, but waiting time increases from task request to execution start and from task completion to result delivery
Solution Approach 1:
The patent implements preliminary action by having processor cores pre-register service requests with the service controller before actual task execution is needed. The symmetrical network interface enables cores to establish communication channels in advance, and the service controller pre-configures task distribution mechanisms. This eliminates waiting time by ensuring that when a core needs to offload a task, the receiving core is already ready and configured to execute it immediately.
Data Source
AI summary
A computer processor comprises: a fetch unit that reads and writes instructions and data, a register file including a plurality of registers, which includes a general-purpose register and a special register, an arithmetic logic unit that performs computational processing, a decoder/controller that interprets the instructions and generates a control signal, a symmetric network interface that includes a master interface and a slave interface and that is connected to an on-chip network; and a service controller that receives a service request from the external source through the on-chip network and the symmetric network interface, that communicates with the decoder/controller to send and receive a state of the service request and a state of the computer processor, and that copies an instruction address of a subroutine for executing the service request to a program counter to perform an operation of a designated code when the decoder/controller determines execution of the service request.