Symmetrical On-Chip Inductor for Differential Circuits
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Solution Overview
Problem
Conventional on-chip inductors in semiconductor integrated circuits are not symmetrical, which makes them unsuitable for differential circuits, leading to increased common mode noise and reduced quality factor in wireless communication chip designs.
Innovation Solution
A symmetrical inductor design is implemented with specific relationships between the line width and line space of conductive lines, such as S=[−W/6+2]×W for line widths not exceeding 9 μm, and S=0.5W for line widths greater than 9 μm, to reduce parasitic capacitance and maintain the usable frequency range in differential operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar spiral inductor or two-level spiral inductor is used, then chip area occupation is reduced and quality factor is improved, but the inductor structure is not symmetrical and cannot suitably prevent common mode noise in differential circuits
Solution Approach 1:
The patent applies asymmetry principle in reverse by deliberately designing a symmetrical inductor structure with four conductive lines arranged symmetrically about a central axis, where first and second conductive lines are symmetrical to each other, and third and fourth conductive lines are symmetrical to each other. This symmetry enables the inductor to function properly in differential circuits by preventing common mode noise, while the specific line width and line space relationships optimize the electrical performance.
2Area of stationary object
If line width is increased to reduce chip area, then area occupation is reduced, but parasitic capacitance increases and quality factor deteriorates
Solution Approach 1:
The patent applies parameter changes by establishing specific relationships between line width and line space: when line width exceeds 6 μm, line space is less than line width; when line width is less than 6 μm, line space exceeds line width; when line width equals 6 μm, line space equals line width. These parameter relationships optimize the balance between area occupation and parasitic capacitance, maintaining quality factor while reducing chip area.
3Quantity of substance
If line space is reduced to increase inductance density, then inductance per area is improved, but parasitic capacitance between adjacent lines increases
Solution Approach 1:
The patent dynamically adjusts line space based on line width parameters to optimize the balance between inductance density and parasitic capacitance. The conditional relationships ensure that narrower lines have larger spacing to minimize capacitance, while wider lines can have reduced spacing to maximize density, achieving optimal inductance per area without excessive parasitic effects.
Data Source
AI summary
A symmetrical inductor. The inductor comprises first, second, third and fourth semi-circular conductive lines disposed in an insulating layer on a substrate, having first and second ends, respectively. The second semi-circular conductive line makes the first semi-circular conductive line symmetric, in which the first ends of the first and second semi-circular conductive lines are electrically connected to each other. The third semi-circular conductive line is parallel to and located outside the first semi-circular conductive line, in which the second ends of the third and second semi-circular conductive lines are electrically connected to each other. The fourth semi-circular conductive line makes the third semi-circular conductive line symmetric, in which the second ends of the fourth and first semi-circular conductive lines are electrically connected to each other. The first, second, third and fourth semi-circular conductive lines have the same line width and the same line space, in which the line space exceeds the line width when the line width is less than 6 μm.