Rotational Symmetrical Overlay Mark for Semiconductor Process Stability
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Solution Overview
Problem
Conventional overlay measurement techniques in semiconductor manufacturing suffer from measurement errors due to asymmetry in patterned line profiles, particularly in x/y direction measurements, which affect the accuracy of process control in self-aligned double patterning (SADP) processes.
Innovation Solution
An overlay mark comprising rotational symmetrical first and second pattern blocks with big and small frames, where the widths of the big frames are at least three times greater than those of the small frames, is integrated into the SADP process to evaluate process stability by measuring variations in pattern dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional overlay measurement techniques are used, then measurement process is simple, but measurement precision deteriorates due to asymmetry in patterned line profiles
Solution Approach 1:
The patent applies asymmetry principle by designing overlay marks with intentional asymmetric structures (e.g., asymmetric bridge patterns, asymmetric frame configurations) that compensate for the asymmetric distortion introduced during SADP manufacturing. The asymmetric design allows the measurement system to distinguish between intentional asymmetric features and measurement artifacts, thereby improving overlay measurement accuracy despite the complex asymmetric structure required
Solution Approach 2:
The overlay mark is segmented into multiple distinct components including separate frame structures, bridge patterns, and reference markers. This segmentation allows different portions of the overlay mark to serve specific measurement functions, enabling precise measurement of overlay errors in different directions while maintaining overall measurement accuracy
2Measurement precision
If rotational symmetrical pattern blocks with significant width difference are used, then measurement precision of pattern dimension variation is improved, but device complexity increases
Solution Approach 1:
The overlay mark incorporates preliminary reference structures (big frames and small frames with known dimensional relationships) that are formed before the actual measurement process. These pre-configured structures with predetermined width ratios (at least 3:1) serve as built-in calibration references, eliminating the need for separate calibration steps and improving measurement precision of pattern dimension variations
Solution Approach 2:
The patent utilizes dimensional relationships by creating frames with significantly different width dimensions (big frames vs. small frames). This dimensional variation provides a built-in reference system where the known width ratio serves as a measurement scale, enabling precise measurement of overlay errors and pattern dimension variations by comparing actual measurements against the known dimensional relationships
Data Source
AI summary
The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.