Symmetrical PCIe Storage Controller Bandwidth
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Solution Overview
Problem
High Performance Computing (HPC) systems face bandwidth limitations in storage subsystem controllers, requiring numerous storage machines to accommodate data output, leading to infrastructure challenges and inefficiencies.
Innovation Solution
A symmetrical PCIe-based storage controller architecture using crossover switches to connect host and storage paths directly to multiple PCIe memory controllers, ensuring equal access and doubling bandwidth compared to prior art.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional block storage machines with limited bandwidth (10-40 GB/s) are used, then the processor complex bandwidth is maintained within current architectural limits, but the number of storage machines required increases significantly to accommodate HPC system output
Solution Approach 1:
The storage controller is divided into multiple independent processor complexes (at least two), each capable of handling storage operations independently. This segmentation allows the system to achieve higher aggregate bandwidth by distributing data paths across multiple processor complexes, thereby reducing the total number of storage machines needed while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from a single-processor complex architecture to a multi-processor complex architecture, adding a dimensional aspect to the storage controller design. This dimensional change enables parallel data processing paths and allows the system to scale bandwidth by adding processor complexes rather than increasing the capacity of a single processor, thus reducing the number of external storage machines required.
2Productivity
If hundreds of block storage machines are deployed to provide sufficient bandwidth, then the write bandwidth requirement for 100% duty cycle burst is met, but infrastructure problems arise including management logistics, MTBF issues, power infrastructures and cabling
Solution Approach 1:
Multiple processor complexes are merged into a single storage controller unit with shared memory and coordinated control. This consolidation achieves high write bandwidth through internal parallelism while reducing infrastructure complexity by combining what would otherwise require multiple separate storage machines into one integrated system, thereby simplifying management, power, and cabling requirements.
Solution Approach 2:
Each processor complex within the storage controller is designed to be universally capable of handling any data path, providing multi-functional capability. This universality allows the system to achieve high bandwidth through flexible resource allocation while reducing infrastructure complexity, as each processor complex can serve multiple functions and data paths rather than requiring dedicated specialized hardware for each function.
3Productivity
If data accesses are routed between two or more processor complexes in prior art storage controllers, then storage operations can be distributed, but restrictions on mapping and accesses are imposed
Solution Approach 1:
The patent creates equipotential conditions by providing equal and direct access from any host bus adapter to any drive path through the shared memory architecture. This eliminates the hierarchical or restricted access patterns of prior art, allowing any processor complex to access any data path with equal efficiency, thereby achieving both high productivity and maximum mapping flexibility without access restrictions.
Solution Approach 2:
Shared memory acts as an intermediary between multiple processor complexes and various data paths, enabling flexible mapping without direct point-to-point connections. This intermediary architecture allows any processor complex to access any data path through the shared memory space, providing adaptability and versatility while maintaining efficient data transfer capability through the mediating memory structure.
Data Source
AI summary
Provided herein are systems, apparatuses and methods (i.e., utilities) that allow for increasing the bandwidth of a processing complex of a storage controller. The utilities utilize a symmetrical approach where PCIe switches overcome limitations of prior art processor complexes. The symmetrical approach provided by the disclosed utilities as incorporated into a storage controller provides equal access from any host path/channel to any drive path/channel (i.e., storage element). More specifically, a first or a first set of PCIe switches connect front-end PCIe host bus adaptors, which are connectable to host systems, to front-end data paths of a plurality of PCIe memory controllers. A second or second set of PCIe switches connect backend host bus adapters, which are connectable to storage elements, to back-end data paths of the plurality of PCIe memory controllers. The symmetrical architecture provides at least twice the bandwidth of prior art architectures.