Symmetrical Pixel Circuits With Connection Lines for Faster Display Driving
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Solution Overview
Problem
Existing display devices experience signal delays due to inefficient data signal transmission paths, which affect display quality and performance.
Innovation Solution
The display device incorporates symmetrical pixel circuits in adjacent rows with shared horizontal power lines and additional connection lines between gate lines, reducing signal transmission path length and optimizing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional data signal transmission paths are used in display devices, then device structure is simple, but signal delay increases affecting display quality
Solution Approach 1:
The patent segments the data signal transmission path by introducing connection lines between adjacent gate lines. Instead of a single long transmission path from the data driver to each pixel, the signal is divided into multiple segments that can be transmitted through different routes (direct data line path or path through connection lines), thereby reducing overall signal delay and addressing the time loss issue without excessive structural complexity.
2Productivity
If symmetrical pixel circuits with additional connection lines are implemented, then signal processing speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetrical layout strategies in specific areas to optimize signal transmission. The connection lines are strategically positioned between adjacent gate lines to create optimized signal paths, while pixel circuits maintain functional symmetry. This selective asymmetry in the connection structure allows faster signal processing without requiring complete redesign of all pixel circuits, thus balancing manufacturing ease with performance improvement.
3Speed
If connection lines are added between gate lines, then signal transmission efficiency improves, but device structure becomes more complex
Solution Approach 1:
The patent utilizes the spatial dimension between adjacent gate lines to route connection lines. Instead of extending data lines horizontally across the display area, the connection lines are routed vertically or diagonally through the space between gate lines, creating a three-dimensional wire routing strategy. This dimensional approach reduces signal transmission distance and improves speed while managing wire layout complexity through efficient use of available spatial dimensions.
Data Source
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AI summary
A display device is disclosed that includes first and second gate lines extending in a first direction and arranged along a second direction. Data lines extend in the second direction and are arranged along the first direction. First pixels are connected to the first gate line in common and the data lines respectively. Second pixels are connected to the second gate line in common and the data lines respectively. Connection lines are disposed between the first and second gate lines, and at least one of the connection lines is connected to a corresponding data line. Each of the first and second pixels includes a light emitting element and a pixel circuit including transistors. The pixel circuit of a first pixel of the first pixels and the pixel circuit of a second pixel of the seconds pixel are symmetrical with respect to a connection line of the connection lines in a plan view.