Memory Clock Duty Cycle Correction Using Symmetrical Pulse Circuits
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Solution Overview
Problem
Existing memory systems face challenges in maintaining optimal duty cycle correction for clock signals, leading to inefficiencies and increased power consumption due to duty errors and variations.
Innovation Solution
A semiconductor integrated circuit with a duty cycle correction (DCC) circuit that includes a duty cycle detector (DCD) and a duty cycle adjuster (DCA) to detect and adjust duty errors in clock signals, using a configuration with symmetrical pulse generators and inversion buffers to generate balanced differential clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a duty cycle correction circuit is used to correct duty ratio between clock signals, then duty cycle accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detector continuously monitors the duty ratio of clock signals and provides detection results to the duty cycle adjuster, which then adjusts the clock signal duty cycles accordingly. This closed-loop feedback system achieves accurate duty cycle correction while optimizing power consumption by only making adjustments when duty errors are detected, rather than continuously operating at full power.
Solution Approach 2:
The patent employs dynamic adjustment of duty cycles through the duty cycle adjuster, which can modify clock signal parameters in real-time based on detection results. The system transitions from static duty cycle values to dynamically adjustable ones, allowing the circuit to adapt to varying conditions and minimize power consumption while maintaining accuracy. The delay elements and signal routing are designed to enable flexible, dynamic control of pulse widths and timing.
2Stability of the object's composition
If duty cycle correction is continuously applied, then clock signal stability is improved, but frequency of corrections increases leading to inefficiency
Solution Approach 1:
The feedback mechanism enables the system to maintain clock signal stability by continuously monitoring duty cycles and making corrections only when deviations are detected. The duty cycle detector compares actual duty ratios against target values and triggers adjustments only when errors exceed thresholds, providing stable operation without requiring constant active correction. This event-driven approach improves efficiency by reducing unnecessary correction operations.
Solution Approach 2:
The duty cycle correction circuit performs self-service by automatically detecting duty errors and triggering its own correction operations without external intervention. The system monitors its own output signals and self-adjusts the duty cycles through the adjuster circuit, maintaining stability while minimizing the need for external control logic or continuous processing, thereby improving overall system efficiency.
3Measurement precision
If complex duty cycle correction operations are performed, then duty error reduction is improved, but installation area increases
Solution Approach 1:
The duty cycle correction function is segmented into distinct modular components: a duty cycle detector that monitors clock signals, a duty cycle adjuster that modifies duty ratios, and delay elements that control timing. This segmentation allows each component to be optimized independently for area efficiency while collectively achieving accurate duty error reduction. The modular structure enables compact layout and reduces overall circuit footprint compared to monolithic implementations.
Solution Approach 2:
The patent achieves duty error reduction by changing parameters of existing circuit elements rather than adding complex new structures. The delay elements adjust pulse widths and timing parameters to correct duty ratios, and the adjuster modifies clock signal characteristics through parameter tuning. This approach reduces installation area by utilizing parameter adjustments in existing components rather than requiring additional complex correction circuitry.
Data Source
AI summary
According to one embodiment, semiconductor integrated circuit includes: first and second pulse generators that generate first and second pulse signals based on a first signal, and third and fourth pulse signal based on a second signal, respectively; first and second inversion buffers that output a third signal based on inputs of the first and third pulse signals, and a fourth signal based on inputs of the second and fourth pulse signal, respectively; wherein, when a logic level of the first or the third pulse signal changes from a first logic level to a second logic level, the first inversion buffer changes a logic level of the third signal, and when a logic level of the second or the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes a logic level of the fourth signal.