Symmetrical Semiconductor Layout for Uniform Parallel Switching
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Solution Overview
Problem
In semiconductor arrangements with multiple elements operating in parallel, uneven current distribution and switching states can lead to reduced lifetime and undesired oscillations due to ohmic resistance and inductance, particularly in fast-switching silicon carbide-based chips.
Innovation Solution
A high symmetrical substrate layout is introduced, with a third/middle row of chips accessed by 3-dimensional interconnects, and a comb-shaped structure on the substrate to ensure simultaneous current flow and isolate groups of semiconductor elements, allowing for efficient utilization of space and reliable switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor elements are electrically connected in parallel to handle higher currents, then the current handling capability is improved, but uneven current distribution and switching state discrepancies occur due to ohmic resistance and inductance
Solution Approach 1:
The patent applies asymmetry by intentionally designing different electrical connection paths for high-side and low-side semiconductor elements. The low-side elements have a common connection point that creates a star topology, while high-side elements have distributed connection points. This asymmetric design compensates for the inherent asymmetry in current flow paths, balancing the total inductance and resistance seen by each semiconductor element and achieving uniform current distribution.
Solution Approach 2:
The patent implements equipotentiality by creating a common electrical connection point for all low-side semiconductor elements, ensuring they all experience the same electrical potential and inductance to ground. This is achieved through a star-shaped connection topology where multiple low-side elements connect to a single central point, eliminating potential differences and ensuring simultaneous switching behavior.
2Reliability
If a third/middle row of chips is introduced to improve symmetry, then the current distribution uniformity is improved, but the device complexity increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar two-row layout to a three-dimensional arrangement with a middle row of semiconductor elements. This vertical stacking approach allows better symmetry in current flow paths without significantly increasing lateral substrate area, as the middle row elements are accessed through 3D interconnect structures that penetrate through the substrate.
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor elements into distinct groups: high-side elements, low-side elements, and middle-row elements. Each group has dedicated electrical connection paths that are independently optimized. The middle row acts as a separate segment that bridges the symmetry gap between high and low side elements, with each segment having its own optimized connection topology.
3Reliability
If 3-dimensional interconnect elements are used to access the third row of chips, then the symmetry and current flow balance are improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing 3D interconnect elements as mediators between the middle row of semiconductor elements and the substrate's electrical connection network. These interconnect structures act as intermediate components that simplify the overall manufacturing process by providing standardized access points, rather than requiring complex custom routing for each middle-row element.
Data Source
AI summary
The present disclosure relates to a semiconductor arrangement, comprising: a substrate; a first group of semiconductor elements forming a first switch; a second group of semiconductor elements forming a second switch. The substrate comprises: a first electrically conductive area; a second electrically conductive area; a third electrically conductive area; a fourth electrically conductive area. The semiconductor arrangement further comprises: a first electrical connection line; a second electrical connection line; and a third electrical connection line. The first electrical connection line, the second electrical connection line, the third electrical connection line and the fourth area of the substrate are dimensioned according to a symmetry criterion to enable a simultaneous current flow through the load paths of the semiconductor elements of the first group as well as a simultaneous current flow through the load paths of the semiconductor elements of the second group.