Symmetrical Substrate Warpage Reduction in PoP Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing warpage and increasing reliability in Package-on-Package (PoP) technology due to coefficient of thermal expansion (CTE) mismatches between different layers, leading to fabrication stresses and reliability risks in high-density integration.
Innovation Solution
The implementation of symmetrical redistribution structures on either side of a core substrate, with conductive connectors like ball grid arrays, provides balanced electrical and mechanical connections, reducing warpage and enhancing reliability by equalizing stresses and allowing for additional buffer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (PoP) technology is used to increase integration density, then component density and functionality are enhanced, but warpage and reliability issues arise due to CTE mismatches between layers
Solution Approach 1:
The patent applies asymmetry by creating an asymmetrical stress compensation structure where a first stress compensation layer is formed on the first substrate and a second stress compensation layer is formed on the second substrate. These layers have different properties and are positioned asymmetrically relative to the core substrate to specifically counteract the CTE mismatches occurring in the PoP structure, thereby reducing warpage while maintaining high integration density
2Productivity
If CTE mismatches between layers are present in PoP structure, then high-density integration is achieved, but fabrication stresses increase leading to reliability risks
Solution Approach 1:
The patent applies parameter changes by modifying the stress compensation layers' material properties, thickness, and positioning to dynamically adjust and balance the stress distribution throughout the PoP structure. By changing these parameters, the system compensates for CTE mismatches and reduces fabrication stresses while maintaining high integration density
Data Source
AI summary
An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.