CMOS Image Sensor Symmetrical Transistor Layout for Sensitivity Uniformity
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Solution Overview
Problem
As pixel size decreases to 1 µm or less in CMOS image sensors, variations in sensitivity among photodiodes occur due to asymmetrical layout configurations of transistor groups, leading to output differences and reduced sensitivity.
Innovation Solution
The solution involves dividing shared transistors into two symmetrical transistor groups with symmetrical layout configurations of gates and source/drain areas, ensuring that the layout patterns and areas of both groups are substantially the same to minimize variations in sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel size is decreased to maximize photodiode numerical aperture, then productivity and light-receiving capability are improved, but sensitivity variations among photodiodes increase due to asymmetrical layout
Solution Approach 1:
The patent applies asymmetry principle in reverse (achieving symmetry) by configuring transistor groups and their associated wiring in substantially identical layouts. Specifically, first and second transistor groups are positioned symmetrically with respect to photodiodes, and wiring connections are made substantially identical in length and routing pattern. This symmetrical arrangement ensures that signal transmission characteristics are uniform across all photodiodes, eliminating sensitivity variations while maintaining small pixel size for high numerical aperture
2Area of stationary object
If pixel size is decreased to 1 µm or less, then device integration density is improved, but sensitivity variations among photodiodes occur due to layout asymmetry
Solution Approach 1:
The patent uses symmetry (reverse application of asymmetry principle) to counteract the sensitivity variations that naturally occur in miniaturized pixels. By arranging transistor groups and their wiring in substantially identical symmetrical configurations, the patent ensures uniform signal characteristics across all photodiodes even at 1 µm pixel size, thereby achieving both high integration density and sensitivity consistency
3Productivity
If transistors are shared among multiple pixels to maximize photodiode area, then productivity is improved, but sensitivity variations increase due to asymmetrical transistor group layouts
Solution Approach 1:
The patent applies symmetry principle to ensure that shared transistor groups produce uniform output signals across multiple pixels. By configuring first and second transistor groups with substantially identical layouts, gate lengths, source/drain dimensions, and wiring patterns, the patent eliminates sensitivity variations that would otherwise result from asymmetrical arrangements, thereby maintaining both high photodiode area utilization and consistent output signals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses sensitivity variations among photodiodes by ensuring uniformity in the layout configurations of transistor groups, improving the consistency of output signals across shared pixel units.
Implementation Method 1
photodiodes that photoelectrically convert incident light
Data Source
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AI summary
A solid-state imaging device includes a plurality of photoelectric conversion units, a floating diffusion unit that is shared by the plurality of photoelectric conversion units and converts electric charge generated in each of the plurality of photoelectric conversion units into a voltage signal, a plurality of transfer units that are respectively provided in the plurality of photoelectric conversion units and transfer the electric charge generated in the plurality of photoelectric conversion units to the floating diffusion unit, a first transistor group that is electrically connected to the floating diffusion unit and includes a gate and source/drain which are arranged with a first layout configuration, and a second transistor group that is electrically connected to the floating diffusion unit, includes a gate and source/drain arranged with a second layout configuration symmetrical to the first layout configuration, and is provided in a separate area from the first transistor group.