Symmetry-Adapted Fermionic Mapping Reduces Qubit Count
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing quantum computing mappings do not efficiently utilize available resources, particularly in simulating quantum-mechanical systems, as they fail to fully exploit the symmetries of the systems, leading to increased computational requirements.
Innovation Solution
The proposed solution involves a symmetry configuration mapping (SCM) method that identifies and utilizes all existing symmetries in the simulated quantum-mechanical systems to minimize the number of qubits required in the quantum processor, thereby creating more compact maps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard quantum computing mappings are used to simulate quantum-mechanical systems, then the simulation can be performed, but the number of qubits required increases and computational resources are not efficiently utilized
Solution Approach 1:
The patent applies asymmetry by breaking the symmetry between different qubit addressing schemes. Instead of treating all qubits equally with uniform addressing, the patent introduces asymmetric addressing patterns that exploit the specific symmetry properties of the simulated quantum system. This asymmetric mapping allows certain qubit configurations to be accessed more efficiently, reducing the total number of qubits needed while maintaining simulation accuracy.
Solution Approach 2:
The patent changes the parameter of qubit addressing scheme from standard uniform addressing to symmetry-adapted asymmetric addressing. By modifying this fundamental parameter of the quantum computing mapping, the system can exploit symmetries in the Hamiltonian to reduce the computational Hilbert space, thereby requiring fewer qubits for the same simulation task.
2Quantity of substance
If mappings that exploit only Z2 symmetries are used, then some resource reduction is achieved, but other symmetries present in the system cannot be accounted for
Solution Approach 1:
The patent implements universality by creating a generalized addressing scheme that can handle multiple types of symmetries (Z2, continuous, discrete, spatial, temporal) within a single unified framework. This multi-functional mapping approach allows the same quantum computer to efficiently simulate various quantum systems with different symmetry properties, making the resource reduction technique broadly applicable across different simulation scenarios.
Solution Approach 2:
The patent introduces dynamics by making the addressing scheme adaptable to different symmetry types. Rather than using a static addressing pattern, the system dynamically selects and applies appropriate symmetry-adapted addressing strategies based on the specific symmetries present in the system being simulated. This dynamic adaptation enables the system to exploit whatever symmetries are available, maximizing resource efficiency for each specific simulation task.
3Ease of manufacture
If independent system mappings are used, then the mapping is simple to define, but the symmetry of the system cannot be fully exploited to minimize computational space
Solution Approach 1:
The patent applies preliminary action by pre-analyzing the symmetry properties of the quantum system before constructing the quantum circuit. The symmetry-adapted addressing scheme is determined in advance based on the system's Hamiltonian symmetries, allowing the mapping to be defined systematically rather than ad hoc. This preliminary symmetry analysis enables the subsequent quantum circuit construction to efficiently exploit these pre-identified symmetries, reducing computational space while maintaining clear definition procedures.
Data Source
AI summary
Systems and methods are provided for mapping arbitrary isolated quantum-mechanical systems to quantum processor registers on quantum computers that use available symmetry to maximize compactness. For example, embodiments of the present disclosure exploit existing symmetries in the simulated system to minimize the required number of quantum bits (qubits) in the quantum processor.