One-Transistor Synapse Cell Circuit for Inference and Weight Updates
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Solution Overview
Problem
One-transistor synapse memory cells face challenges in facilitating inference and update operations within large neural networks due to the need for additional circuitry to mitigate non-ideal effects such as asymmetric updates.
Innovation Solution
The implementation of a memory circuit with a plurality of word lines, bit lines, and signal lines, featuring single memory transistor synapse cells with a pulse shaping unit, logic gate, and pass gate arrangement, which cooperatively apply pulses for weight adjustment during updates and interconnect the memory transistor to bit lines during inference operations, enhancing the functionality of one-transistor synapse cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry is added to one-transistor synapse memory cells to facilitate read and update operations within large networks, then the functionality and reliability of the synapse cell is improved, but the device complexity increases
Solution Approach 1:
The synapse cell circuit is segmented into distinct functional blocks: a logic gate unit for controlling operations, a pulse shaping unit for generating appropriate voltage pulses, and a pass gate arrangement for selective connectivity. This segmentation allows each unit to perform its specific function efficiently while maintaining overall system reliability without excessive complexity.
Solution Approach 2:
The logic gate unit is designed to universally control both read and update operations through a single integrated structure. The same logic gate arrangement handles different operational modes (read, update, reset) by receiving different control signals, eliminating the need for separate dedicated circuits for each function and thereby reducing overall device complexity.
2Measurement precision
If conventional analog inference schemes are used, then the implementation is simpler, but the precision and accuracy of neural network computations deteriorates
Solution Approach 1:
A digital-to-analog converter (DAC) is introduced as an intermediary component that translates digital weight values into analog voltages for the memory transistor gate. This intermediary enables precise digital control over analog weights, achieving high computation accuracy while maintaining compatibility with simple one-transistor memory cell structures. The DAC acts as a bridge between the digital control domain and analog computation domain.
Solution Approach 2:
The circuit incorporates feedback mechanisms where the output of the synapse cell is fed back through the logic gate unit to adjust and refine the weight values. This feedback loop enables iterative optimization of computational accuracy by comparing actual outputs with desired targets and making precise adjustments to the analog weights through the DAC, thereby improving measurement precision without requiring fundamentally more complex circuitry.
3Reliability
If asymmetric update effects are present in one-transistor synapse cells, then the manufacturing and operation remains simple, but the reliability and performance of weight adjustment deteriorates
Solution Approach 1:
The logic gate unit employs an asymmetric control scheme where different control signals are applied to the gate based on the desired update direction (increment or decrement). By using asymmetric voltage levels and timing for upward versus downward weight adjustments, the circuit compensates for inherent asymmetric update effects in the one-transistor memory cell, ensuring reliable and accurate weight modulation without requiring symmetric complex compensation circuits.
Data Source
AI summary
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.