One-Transistor Synapse Cell Circuit for Symmetric Weight Updates
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Solution Overview
Problem
One-transistor synapse memory cells face challenges in facilitating read and update operations within large neural networks and suffer from non-ideal effects such as asymmetric updates, which hinder efficient neuromorphic computation.
Innovation Solution
The implementation of a circuit design that includes a plurality of word lines, bit lines, signal lines, and single memory transistor synapse cells, with a pulse shaping unit, logic gate, and pass gate arrangement to apply pulses for weight adjustment during updates and interconnect memory transistors during inference operations, enhancing the functionality of one-transistor synapse cells by providing feedback for more ideal updating and utilizing both analog and digital inference schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional circuitry is added to the one-transistor synapse cell to facilitate read and update operations, then the functionality for neural network operations is improved, but the device complexity increases
Solution Approach 1:
The circuit design implements multi-functionality by using the same basic circuit structure to perform both read operations (via bit line current measurement) and update operations (via pulse generation and feedback). The logic gate and pass gate arrangement serve dual purposes in controlling both inference and weight adjustment functions within a single synapse cell unit.
2Productivity
If the one-transistor synapse cell is used for neuromorphic computation, then the efficiency is improved, but non-ideal effects such as asymmetric update occur
Solution Approach 1:
The circuit employs feedback mechanisms where the output of the logic gate is fed back through the pass gate arrangement to control the pulse shaping unit. This feedback loop enables the circuit to monitor and adjust the weight update process, compensating for asymmetric effects and ensuring more ideal symmetric weight adjustments during learning operations.
Solution Approach 2:
The pulse shaping unit dynamically changes voltage parameters applied to the memory transistor gate based on feedback signals. By adjusting pulse amplitude, width, and timing parameters, the circuit compensates for asymmetric update effects and achieves more ideal symmetric weight modifications while maintaining computational efficiency.
3Adaptability or versatility
If pulses are applied to the gate of the memory transistor for weight adjustment, then the weight updating capability is improved, but the circuit operation complexity increases
Solution Approach 1:
The pulse shaping unit acts as an intermediary between the logic gate output and the memory transistor gate. It receives control signals from the logic gate and transforms them into appropriately shaped pulses with correct amplitude, width, and timing characteristics, simplifying the overall control architecture while enabling precise weight adjustment.
Solution Approach 2:
The circuit performs preliminary pulse shaping and conditioning before applying voltages to the memory transistor gate. The pulse shaping unit prepares the control pulses in advance with the required characteristics, ensuring proper weight adjustment while reducing the complexity of real-time control operations during inference and learning phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient inference and update functions in large neuron networks, reduces non-ideal effects like asymmetric updates, and improves weight updating and inference processes, particularly in deep neural networks, by leveraging Ferroelectric FETs and feedback mechanisms.
Implementation Method 1
synapse unit cells based on one-transistor memory cell, e.g., Ferroelectric FET (FeFET)
Data Source
AI summary
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.