Synapse Circuit Memory With Variable Resistance
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Solution Overview
Problem
Current SRAM or DRAM-based hardware systems for machine learning applications are limited by slow data throughput and energy inefficiency, especially for large memory arrays, and subthreshold operation techniques introduce unreliable data variations.
Innovation Solution
A synapse circuit with memory that includes a controlled variable resistance and a switch, allowing for high parallelism in readout operations without compromising data reliability, using a controlled variable resistance with a large on-off ratio and a memory cell for storing weight variables, which can be digital or analog, and implemented in a array structure with multiple synapse circuits organized in rows and columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If subthreshold operation or degeneration of bit cells is used to introduce parallelism, then throughput is improved, but data reliability deteriorates due to high variability and unreliability
Solution Approach 1:
The patent changes the operating parameters by using controlled variable resistance elements that can switch between distinct resistance states (high and low) based on stored weight values. This allows the system to operate in a controlled manner with defined resistance levels rather than relying on subthreshold analog operations, thereby maintaining both parallelism for high throughput and discrete state stability for data reliability.
Solution Approach 2:
The patent replaces the traditional subthreshold voltage-based operation with a resistance-based operation using controlled variable resistance elements. This substitution enables the system to achieve parallelism through controlled resistance switching rather than relying on subthreshold effects, thereby improving both throughput and reliability by using more stable resistance states.
2Quantity of substance
If SRAM or DRAM memory structures are used, then data storage is achieved, but energy efficiency deteriorates due to limited energy efficiency in large memory arrays
Solution Approach 1:
The patent merges the memory storage function with the computation function by integrating memory cells directly with the controlled variable resistance elements and switch circuits. This memory-computation integration eliminates the need for separate SRAM/DRAM arrays and associated readout circuitry, thereby achieving high memory capacity while dramatically improving energy efficiency through in-memory computing operations.
Solution Approach 2:
The patent creates a multi-functional synapse circuit that simultaneously performs memory storage (via memory cells), weight encoding (via controlled variable resistance), switching control (via controlled switches), and analog computation (via current flow through resistance networks). This universal circuit design replaces multiple separate components (SRAM/DRAM arrays, sense amplifiers, readout circuits) with a single integrated structure that achieves both high capacity and energy efficiency.
3Productivity
If more synapse circuits are connected to common read bitlines to increase parallelism, then throughput is improved, but read bitline saturation occurs leading to measurement precision deterioration
Solution Approach 1:
The patent segments the readout operation into two distinct phases: a precharge phase where bitlines are prepared with reference voltages, and a measurement phase where controlled switches selectively connect synapse circuits to bitlines based on stored weight values. This segmentation allows multiple synapse circuits to be connected to common bitlines during the measurement phase without saturation, as the controlled switches ensure that only relevant circuits contribute to the bitline current, thereby maintaining both high throughput and readout accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast, energy-efficient, and reliable high-throughput data processing for machine learning applications, achieving improved silicon area usage and low power consumption without saturating read bitlines, even with a large number of synapse circuits.
Implementation Method 1
The controlled variable resistance has an associated first resistance value, when a signaling level associated with a received activation signal is crossing a pre-determined first threshold in a first direction. The controlled variable resistance also has an associated second resistance value, when the signaling level is crossing a pre-determined second threshold in a second direction, opposite to the first direction.
Implementation Method 2
a memory cell for storing a weight variable... A weight variables stored in the memory cell may be a digital or an analog weight variable
Implementation Method 3
a controlled switch... with a control terminal operatively connected to the memory cell for applying the stored weight variable to the control terminal of the controlled switch
Implementation Method 4
a current which is flowing through the controlled switch and the controlled variable resistance... is indicative of a weighted applied activation signal if the controlled variable resistance is adopting the associated first resistance value. Here, the weighting of the applied activation signal is by the stored weight variable.
Data Source
AI summary
A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.