One-Transistor Synapse Cell Circuit for Inference and Weight Adjustment
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Solution Overview
Problem
One-transistor synapse memory cells face challenges in facilitating read and update operations within large networks and suffer from non-ideal effects such as asymmetric updates, which hinder efficient neuromorphic computation.
Innovation Solution
The implementation of a circuit design featuring a plurality of word lines, bit lines, signal lines, and single memory transistor synapse cells, with pulse shaping units, logic gates, and pass gates to apply pulses for weight adjustment during updates and interconnect memory transistors during inference operations, enhancing the functionality of one-transistor synapse cells by providing feedback for improved updating and utilizing digital inference schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional circuitry is added to facilitate read and update operations, then the functionality for large network operations is improved, but the device complexity increases
Solution Approach 1:
The circuit design implements multi-functionality by enabling the same synapse cell to perform both inference operations (reading weight values) and update operations (adjusting weights) through a unified set of circuitry components. The pass gate arrangement and pulse shaping unit serve dual purposes in both operational modes, reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The circuit is segmented into distinct functional blocks including the logic gate for control, pulse shaping unit for signal conditioning, and pass gate arrangement for signal routing. This segmentation allows each component to be optimized independently while maintaining overall system functionality, making the complex operations manageable through modular design.
2Ease of manufacture
If conventional analog inference schemes are used, then the implementation is simple, but the precision and reliability of weight adjustment is degraded due to asymmetric updates
Solution Approach 1:
The circuit incorporates feedback mechanisms where the state of the memory transistor is read and used to control subsequent update operations. The logic gate receives inputs from both word lines and bit lines, processes this feedback information, and generates appropriate control signals for the pulse shaping unit, ensuring that weight adjustments are based on actual cell state and maintaining symmetry in update operations.
Solution Approach 2:
The invention changes the operational parameters by using digitally controlled pulse widths and amplitudes instead of purely analog signals. The pulse shaping unit generates precisely controlled voltage pulses with adjustable duration and magnitude, allowing for symmetric and reliable weight adjustments by manipulating pulse parameters rather than relying on analog voltage levels alone.
3Measurement precision
If digital inference schemes with binary inputs and analog weights are used, then the measurement precision is improved, but the device complexity increases due to additional circuitry requirements
Solution Approach 1:
The circuit employs asymmetric design where the input side accepts digital binary signals while the weight storage and output side maintains analog characteristics. This asymmetry allows precise digital control and measurement while preserving the continuous weight values needed for neuromorphic computation, achieving high measurement precision without requiring fully digital or fully analog circuitry throughout.
Data Source
AI summary
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.