Synaptic C-DAC Circuit With Parasitic Capacitance Correction

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Solution Overview

Problem

Spike neural networks (SNNs) experience calculation errors due to charge discrepancies caused by parasitic capacitance and current sources in synapses, leading to inaccuracies in neural network operations.

Innovation Solution

A synaptic circuit is designed with a current-mode digital-to-analog converter (C-DAC) circuit, a parasitic capacitor correction circuit, and a pre-discharge circuit to manage and correct parasitic capacitance, ensuring uniform charge calculation by adjusting switch states based on weight values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a C-DAC circuit is used to supply current based on weight values in an SNN, then the neural network operation speed is improved, but calculation errors occur due to parasitic capacitance causing charge sharing

Engineering Contradiction:

Improveneural network operation speedVSAvoidcharge calculation accuracy

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The patent converts the harmful parasitic capacitance into a beneficial element by introducing a correction circuit that deliberately adds an equal amount of parasitic capacitance. This correction circuit uses the same physical phenomenon (parasitic capacitance) to counterbalance the error caused by the C-DAC circuit's parasitic capacitance, thereby improving charge calculation accuracy while maintaining high-speed operation

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent implements a feedback mechanism where the weight value control signals are fed back to the parasitic capacitor correction circuit. This feedback allows the correction circuit to dynamically adjust its parasitic capacitance based on the actual weight values being processed, ensuring continuous compensation for charge sharing errors and maintaining calculation precision throughout operation

Inventive Principle:

Principle #23Feedback

2Device complexity

If parasitic capacitance is present in the C-DAC circuit, then the circuit complexity is reduced, but charge sharing occurs between parasitic capacitance and membrane capacitance causing calculation errors

Engineering Contradiction:

Improvecircuit complexityVSAvoidneural network operation accuracy

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Instead of eliminating parasitic capacitance through complex shielding or compensation networks, the patent accepts the inherent parasitic capacitance and introduces a matching correction circuit that uses an equal amount of parasitic capacitance to balance the charge sharing effect. This approach maintains circuit simplicity while improving reliability by converting the harmful charge sharing into a balanced, predictable behavior

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Measurement precision

If switches in the C-DAC circuit are opened or closed based on weight values, then current supply accuracy is improved, but parasitic capacitance varies causing charge calculation errors

Engineering Contradiction:

Improvecurrent supply accuracyVSAvoidparasitic capacitance consistency

Core Design Contradiction:

Measurement precisionVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by pre-configuring the parasitic capacitor correction circuit with switches that are controlled by inverted weight values. This preliminary setup ensures that the correction circuit is ready to compensate for parasitic capacitance variations before the actual neural network operation begins, maintaining both current supply accuracy and parasitic capacitance consistency throughout the computation process

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution minimizes calculation errors by maintaining consistent capacitor capacity, preventing charge sharing and ensuring accurate neural network operations in SNNs.

Implementation Method 1

a current-mode digital-to-analog converter (C-DAC) circuit that receives the weight value from the weight memory and supplies a current based on the weight value

Methodology Applied

Scientific EffectCurrent-mode digital-to-analog conversion:

Implementation Method 2

a parasitic capacitor correction circuit that receives the weight value from the weight memory and to correct a value of parasitic capacitance generated by the C-DAC circuit based on the weight value

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 3

a pre-discharge circuit that drains charges accumulated by the parasitic capacitance

Methodology Applied

Scientific EffectCharge discharge:

Data Source

PatentUS12585925B2Sysnapse circuit for preventing errors in charge calculation and spike neural network circuit including the same

Publication Date: 2026.03.24 ELECTRONICS & TELECOMM RES INST

AI summary

Disclosed is a synaptic circuit including a weight memory that stores a weight value, a current-mode digital-to-analog converter (C-DAC) circuit that receives the weight value from the weight memory and supplies a current based on the weight value, a parasitic capacitor correction circuit that receives the weight value from the weight memory and to correct a value of parasitic capacitance generated by the C-DAC circuit based on the weight value, and a pre-discharge circuit that drains charges accumulated by the parasitic capacitance.