Synaptic Element Conductance Control via Memory Cell Segmentation
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Solution Overview
Problem
Current artificial synaptic elements in semiconductor memory arrays lack controllable and reproducible gradual resistance changes necessary for simulating biological synapses in neuromorphic systems, with existing RRAM and PRAM technologies exhibiting asymmetry and insufficient distinguishability in resistance states.
Innovation Solution
A memory apparatus with a memory array of selectively programmable memory cells, bit lines, and word lines, where a controller applies writing and reading voltages to determine synaptic weights by summing currents through selected memory cells, allowing for linear and proportional resistance changes, enabling the operation of memory cells as synaptic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If RRAM or PRAM elements are used to implement artificial synaptic elements, then resistance states can be distinguished and stored, but the resistance changes are asymmetric and lack reproducibility
Solution Approach 1:
The patent divides a single synaptic element into multiple memory cells (e.g., 4 memory cells) that work together. Each memory cell contributes to the overall conductance, and by controlling the number of memory cells in parallel, the system achieves reproducible gradual conductance changes. This segmentation approach transforms the unreliable single-cell resistance change into a reliable multi-cell collective behavior.
Solution Approach 2:
The patent combines multiple memory cells to form a single functional synaptic element. The conductance of the synaptic element is determined by the parallel combination of multiple memory cell conductances, enabling gradual and reproducible conductance modulation. This merging of multiple cells compensates for the asymmetry and irreproducibility of individual cell resistance changes.
2Ease of manufacture
If digital on/off resistance change is implemented in memory arrays, then logic states can be stored, but gradual and controllable resistance states cannot be achieved
Solution Approach 1:
The patent transforms the static digital on/off state into a dynamic gradual conductance state by controlling the number of active memory cells. The synaptic weight is not fixed but can be dynamically adjusted by programming different numbers of memory cells to be in the low resistance state, enabling continuous analog-like behavior from discrete digital building blocks.
Solution Approach 2:
The patent changes the effective conductance parameter of the synaptic element by varying the number of memory cells in parallel. Instead of changing the resistance of a single cell continuously, the system discretely adjusts the total conductance by including or excluding individual memory cells, achieving gradual conductance change through parameter variation at the system level.
3Reliability
If multiple memory cells are used to achieve gradual conductance change, then reproducibility improves, but device complexity increases
Solution Approach 1:
The patent makes memory cells serve dual functions: they act as both storage elements and conductance contributors. The same memory cells that store digital data are also used to provide the analog conductance values for synaptic weights. This multi-functionality reduces the need for separate components and simplifies the overall system architecture despite using multiple cells per synaptic element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a synaptic element capable of controlling gradual resistance changes with high linearity, enabling accurate determination of synaptic weights and suitable for implementing neuromorphic systems with improved reproducibility and control.
Implementation Method 1
a memory array including a plurality of memory cells capable of selectively storing logic states
Implementation Method 2
determine synaptic weights through a sum of currents flowing through the one or more memory cells
Data Source
AI summary
A memory apparatus includes a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects one or more memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.